AN2727 Freescale Semiconductor / Motorola, AN2727 Datasheet - Page 23

• Manufacturer Part Number: AN2727
• Description: Designing Hardware for the HCS12 D-Family
• Manufacturer: Freescale Semiconductor / Motorola

HCS12 Core I/O Ports
Ports A, B and K can be used as GPIO. In expanded modes these ports form the expanded address and
data bus. Registers for these ports are located in HCS12 core.
Much of Port E can be used for GPIO. In expanded mode, Port E pins support bus control signals. A
number of Port E pins have additional control and configuration functions.
XIRQ (Port E.0) supports a level sensitive, non-maskable interrupt vector. It also can wake the device
from STOP or WAIT without generating an interrupt vector if the X flag in the CCR is = 1.
IRQ (Port E.1) supports a level-sensitive or falling-edge-sensitive, maskable interrupt vector.
Functions related to Port E are configured in the core Port E Assignment Register (PEAR).
Pull-up control bits for the core I/O ports are in the core Pull-up Control Register (PUCR). Not all pins on
Port E have pull devices.
HCS12 Analog Ports
Ports AD0 and AD1 have analog and digital input functionality. Registers for these ports are located in the
two 8-channel analog to digital modules, ATD0 and ATD1. An Input Enable Mask Register (ATDxDIEN)
allows each digital input buffer to be enabled / disabled on a per pin basis. This means that reading the
digital port will not affect pins assigned as analog inputs. There are no internal pull devices available on
these ports.
If the ATD module is not enabled, the status of the ATD input stage will depend solely on the status of the
ATDxDIENx bits.
For electrically noisy environments, it is advisable to connect any unused ATD inputs to ground.
Analog conversion sequences can convert from one to eight channels at a time starting at any one of the
channels. An analysis of the ATD sources to be converted may help utilize the flexibility of the ATD control
and conversion structure. Sources with similar requirements can then be grouped onto adjacent ATD
inputs, and the ATD configured appropriately for each conversion sequence.
The ATD converter’s accuracy is limited by the accuracy of the reference potentials. Noise on the
reference potentials will result in noise on the digital output data stream; the reference potential lines do
not reject reference noise. Ideally the reference supply and ground should be routed separately back the
external 5V voltage source.
The reference pins must have a low AC impedance path back to the source. They are practically a static
load, and a good bypass capacitor (10 nF or larger) will suffice in most cases. In extreme cases, where
high frequency noise is present, series inductors and/or ferrite beads may be necessary, but the ESR
should be kept low. Series resistance is undesirable since each enabled ATD module will draw ~ 375 µA
from the reference. A potential drop across any series resistance will result in gain and offset errors in the
Freescale Semiconductor
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With the ATDxDIENx bit = 0, the digital input stage is disabled. Unconnected input will have no
effect.
With ATDxDIEN = 1, the digital input stage is connected to the pin and an external pull device or
drive should be connected.
Designing Hardware for the HCS12 D-Family, Rev. 0
Pin Considerations — General Purpose I/O
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