AN2727 Freescale Semiconductor / Motorola, AN2727 Datasheet - Page 11

• Manufacturer Part Number: AN2727
• Description: Designing Hardware for the HCS12 D-Family
• Manufacturer: Freescale Semiconductor / Motorola

The logic level must be clearly defined at reset to select the oscillator configuration appropriate to the
external oscillator component layout. This is a common cause of unexpected behavior of the oscillator,
especially where the application also uses Port E.7 as GPIO following reset.
As this is an input with a pull-up device during reset, if the pin is left floating the default configuration is for
a Colpitts oscillator circuit on EXTAL and XTAL; however, it is recommended to tie this pin externally in
electrically noisy environments.
Port E.6 : MODB and Port E.5: MODA
These are GPIO pins that are also used to select the MCU operating mode on reset.
The states of these pins are latched to the MODA and MODB bits at the rising edge of RESET, to
configure the operating mode of the device.
These pins should = 0V at reset to select single chip mode. They have internal pull-downs, active only
when reset is low; so, if left floating, the default configuration is for single chip mode; however, it is
recommended to tie them externally in electrically noisy environments.
Port E.4 : ECLK
In all modes except normal single chip mode, this pin defaults to ECLK (the bus clock).
The ECLK signal can be useful for debugging (ECLK output can also be enabled in normal single chip
mode). Consider adding a test point on this signal, but be aware that it is a relatively high frequency clock
line.
Port E.1 : IRQ
PE1 is a general purpose input pin and optional maskable interrupt request input that can provide a
means of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT
mode. By default this interrupt input is active low level sensitive but can be configured in software to falling
edge sensitive.
Freescale Semiconductor
Take care reading the documentation when determining the polarity of the
XCLKS pin. It is possible for different HCS12 families to have alternative
polarity on this pin for oscillator selection. The block user guide for the
oscillator refers to the XCLKS signal; this is an active high signal. On the
D-family, the pin is XCLKS, an active low input, which must be pulled low
to assert the XCLKS signal to the oscillator module.
Take care when using Port E.4 as a GPIO in single chip mode. The reset
default of this pin is as an input in normal single chip mode and to output
(with the bus clock on it) in special single chip mode. Special single chip
mode is enabled whenever a debug cable is connected and a reset
performed.
Designing Hardware for the HCS12 D-Family, Rev. 0
CAUTION
CAUTION
Pin Considerations Collection – Control
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