FDC37M81x SMSC Corporation, FDC37M81x Datasheet - Page 127
FDC37M81x
Manufacturer Part Number
FDC37M81x
Description
PC98/99 Compliant Enhanced Super I/O Controller
Manufacturer
SMSC Corporation
Datasheet
1.FDC37M81X.pdf
(198 pages)
- Current page: 127 of 198
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When writing to the command and data port with hardware speedup, the IOW timing shown in the figure
titled “IOW Timing for Port 92” in the Timing Diagrams Section is used. This setup time is only required to
be met when using hardware speedup; the data must be valid a minimum of 0 nsec from the leading edge
of the write and held throughout the entire write cycle.
nIOW+n60=B
64=I/O Addr
60=I/O Addr
nAfterD1+B
nIOW+n64
nAfterD1
AfterD1
nCNTL
nIOW'
nAEN
nIOW
nDD1
GA20
AEN
DD1
CLK
D[1]
n64
n60
nA
0ns
Gate A20 Turn-On Sequence Timing
250ns
127
500ns
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