FDC37M81x SMSC Corporation, FDC37M81x Datasheet - Page 131

• Manufacturer Part Number: FDC37M81x
• Description: PC98/99 Compliant Enhanced Super I/O Controller
• Manufacturer: SMSC Corporation

The FDC37M81x implements a group nSMI
output pin. The System Management Interrupt is
a non-maskable interrupt with the highest priority
level used for transparent power management.
The nSMI group interrupt output consists of the
enabled interrupts from each of the functional
blocks in the chip. The interrupts are enabled
onto the group nSMI output via the SMI Enable
Registers 1 and 2.
enabled onto the group nSMI output frame in the
Serial IRQ stream via bit[6] in the SMI Enable
Register 2.
The logic equation for the nSMI output is as
follows:
nSMI
REGISTERS
The following registers can be accessed when in
configuration
Registers B4-B7 and when not in configuration
they can be accessed through the Index and
Data Register (refer to Table 46B).
=
(EN_U2INT
(EN_U1INT
(EN_FINT and IRQ_FINT) or (EN_WDT
and IRQ_WDT) or (EN_MINT and
IRQ_MINT)
IRQ_KINT)
IRQ_IRINT)
(EN_PINT
mode
The nSMI output is then
at
and
and
or
or
and
SYSTEM MANAGEMENT INTERRUPT (SMI)
Logical
(EN_IRINT
(EN_KINT
IRQ_U2INT)
IRQ_U1INT)
IRQ_PINT)
Device
and
and
or
or
or
8,
131
SMI Enable Registers
SMI Enable Register 1
(Configuration Register B4, Logical Device 8)
This register is used to enable the different
interrupt sources onto the group nSMI output.
SMI Enable Register 2
(Configuration Register B5, Logical Device 8)
This register is used to enable additional interrupt
sources onto the group nSMI output. This
register is also used to enable the group nSMI
output frame onto the nSMI Serial IRQ stream
and the routing of 8042 P12 internally to nSMI.
SMI Status Registers
SMI Status Register 1
(Configuration Register B6, Logical Device 8)
This register is used to read the status of the SMI
input events.
whether or not the interrupt is enabled onto the
group SMI output.
SMI Status Register 2
(Configuration Register B7, Logical Device 8)
Note: The status bit gets set