FDC37M81x SMSC Corporation, FDC37M81x Datasheet - Page 36

• Manufacturer Part Number: FDC37M81x
• Description: PC98/99 Compliant Enhanced Super I/O Controller
• Manufacturer: SMSC Corporation

from the host and ranges from 1 to 16.
parameter FIFOTHR, which the user programs, is
one less and ranges from 0 to 15.
A low threshold value (i.e. 2) results in longer
periods of time between service requests, but
requires faster servicing of the request for both
read and write cases.
from (to) the FIFO until empty (full), then the
transfer request goes inactive. The host must be
very responsive to the service request. This is the
desired case for use with a "fast" system.
A high value of threshold (i.e. 12) is used with a
"sluggish" system by affording a long latency
period after a service request, but results in more
frequent service requests.
Non-DMA Mode - Transfers from the FIFO to the
Host
The interrupt and RQM bits in the Main Status
Register are activated when the FIFO contains
(16-<threshold>) bytes or the last bytes of a full
sector have been placed in the FIFO.
interrupt can be used for interrupt-driven systems,
and RQM can be used for polled systems. The
host must respond to the request by reading data
from the FIFO. This process is repeated until the
last byte is transferred out of the FIFO. The FDC
will deactivate the interrupt and RQM bit when the
FIFO becomes empty.
Non-DMA Mode - Transfers from the Host to the
FIFO
The interrupt and RQM bit in the Main Status
Register are activated upon entering the execution
phase of data transfer commands. The host must
respond to the request by writing data into the
FIFO. The interrupt and RQM bit remain true until
the FIFO becomes full. They are set true again
when the FIFO has <threshold> bytes remaining in
the FIFO. The interrupt will also be deactivated if
TC and nDACK both go inactive. The FDC enters
the result phase after the last byte is taken by the
FDC from the FIFO (i.e. FIFO empty condition).
DMA Mode - Transfers from the FIFO to the Host
The host reads (writes)
The
The
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The FDC activates the DDRQ pin when the FIFO
contains (16 - <threshold>) bytes, or the last byte
of a full sector transfer has been placed in the
FIFO. The DMA controller must respond to the
request by reading data from the FIFO. The FDC
will deactivate the DDRQ pin when the FIFO
becomes empty.
nDACK goes active for the last byte of a data
transfer (or on the active edge of nIOR, on the last
byte, if no edge is present on nDACK). A data
underrun may occur if FDRQ is not removed in
time to prevent an unwanted cycle.
DMA Mode - Transfers from the Host to the FIFO.
The FDC activates the FDRQ pin when entering
the execution phase of
commands. The DMA controller must respond by
activating the nDACK and nIOW pins and placing
data in the FIFO. FDRQ remains active until the
FIFO becomes full. FDRQ is again set true when
the FIFO has <threshold> bytes remaining in the
FIFO. The FDC will also deactivate the FDRQ pin
when TC becomes true (qualified by nDACK),
indicating that no more data is required. FDRQ
goes inactive after nDACK goes active for the last
byte of a data transfer (or on the active edge of
nIOW of the last byte, if no edge is present on
nDACK). A data overrun may occur if FDRQ is
not removed in time to prevent an unwanted cycle.
Data Transfer Termination
The FDC supports terminal count explicitly through
the
underrun/overrun
functions.
parameter can define the last sector to be
transferred in a single or multi-sector transfer.
If the last sector to be transferred is a partial
sector, the host can stop transferring the data in
mid-sector, and the FDC will continue to complete
The only difference between these implicit
functions and TC is that they return "abnormal
termination" result status. Such status indications
can be ignored if they were expected.
the sector as if a hardware TC was received.
TC
pin
For full sector transfers, the EOT
and
and
FDRQ goes inactive after
implicitly
end-of-track
the data transfer
through
(EOT)
the