FDC37M81x SMSC Corporation, FDC37M81x Datasheet - Page 146

• Manufacturer Part Number: FDC37M81x
• Description: PC98/99 Compliant Enhanced Super I/O Controller
• Manufacturer: SMSC Corporation

Note 1: This chip uses ISA address bits [A11:A0] to decode the base address of each of its logical
Note 2: The Configuration Port is at either 0x03F0 or 0x0370 (for SYSOPT=0 or SYSOPT=1) at power up
LOGICAL
NUMBER
DEVICE
Config.
0x06
0x07
0x08
0x09
Port
devices. Bit 6 of the OSC Global Configuration Register (CR24) must be set to ‘1’ and Address
Bits [A15:A12] must be ‘0’ for 16-bit address qualification.
and can be relocated via the global configuration registers at 0x26 and 0x27.
Auxilary I/O
LOGICAL
Reserved
Reserved
DEVICE
Config.
KYBD
Port
Table 55 - I/O Base Address Configuration Register Description
REGISTER
0x26,0x27
(Note 2)
INDEX
n/a
n/a
n/a
ON 2 BYTE BOUNDARIES
Fixed Base Address: 60,64
[0x0100:0x0FFE]
Not Relocatable
146
BASE I/O
(NOTE 1)
RANGE
n/a
n/a
+0 : Data Register
+4 : Command/Status Reg.
n/a
n/a
See Configuration Registers in
Table 51. Accessed through the
INDEX and DATA Ports located
at the Configuration Port
Address and the Configuration
Port Address +1 respectively.
BASE OFFSETS
FIXED