VG3617161ET-6 Powerchip, VG3617161ET-6 Datasheet - Page 11

• Manufacturer Part Number: VG3617161ET-6
• Description: 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
• Manufacturer: Powerchip

Note 1. All entries assume that CKE was active (High level)during the preceding clock cycle.
VIS
Current state
Write
recovering
Write
recovering
with auto
precharge
Refreshing
Mode register
accessing
Document:1G5-0189
10. IIIegal if t
2. If both banks are idle, and CKE is inactive(Low level), the device will enter Power down mode.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),
4. If both banks are idle, and CKE is inactive(Low level), the device will enter Self refresh mode.
5. IIIegal if t
6. IIIegal if t
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data if t
All input buffers except CKE will be disabled.
depending on the state of that bank.
All input buffers except CKE will be disabled.
RCD
RAS
RRD
is not satisfied.
CS
is not satisfied.
is not satisfied.
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS
X
H
H
H
H
X
H
H
H
H
X
H
H
X
H
H
H
L
L
L
L
L
L
L
L
L
L
L
DPL
CA
X
H
H
H
H
X
H
H
H
H
X
H
H
X
H
H
X
L
L
L
L
L
L
L
L
L
L
L
is not satisfied.
WE
H
H
H
H
H
H
H
H
H
X
L
L
L
L
X
L
L
L
L
X
X
X
X
X
X
L
X
X
Address
X
X
X
BA,CA,A10
BA,CA,A10
BA,RA
BA,A10
X
Op-Code
X
X
X
BA,CA,A10
BA,CA,A10
BA,RA
BA,A10
X
Op-Code
X
X
X
X
X
X
X
X
X
X
Rev.2
Command
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
PEF/SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
REF/PALL
REF/SELF
MRS
DESL
NOP/BST
READ/WRIT
ACT/PRE/PALL
REF/SELF/MRS
DESL
NOP
BST
READ/WRITE
ACT/PRE/PALL/
REF/SELF/MRS
CMOS Synchronous Dynamic RAM
Action
Start read, Determine AP
New write, Determine AP
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop
Nop
Nop
Nop
Nop
Nop
Nop
Nop
Nop
Nop










Enter
Enter
Enter
Enter
Enter
Enter
Enter
Enter
Enter
Enter
precharge after t
row active after t
row active after t
row active after t
precharge after t
precharge after t
idle after t
idle after t
idle after 2 Clocks
idle after 2 Clocks
1,048,576 x 16 - Bit
Page 11
RC
RC
VG3617161ET
DPL
DPL
DPL
DPL
DPL
DPL
8
3
3
3,8
3
3
3
Notes
(3/3)