VG3617161ET-6 Powerchip, VG3617161ET-6 Datasheet - Page 24

• Manufacturer Part Number: VG3617161ET-6
• Description: 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
• Manufacturer: Powerchip

VIS
PRECHARGE TERMINATION in READ Cycle
Document:1G5-0189
10.2 PRECHARGE TERMINATION
CAS latency=1
DQ
Command
CAS latency=2
DQ
CAS latency=3
DQ
CLK
Command
command
10.2.1 PRECHARGE TERMINATION in READ Cycle
command. When the PRECHARGE command is asserted, the BURST READ operation is termi-
nated and PRECHARGE starts.
two clocks(CAS latency of 3) after the PRECHARGE command and the same bank can be acti-
vated again after t
During a READ cycle, the BURST READ operation can be terminated by a PRECHARGE
Read data will remain valid until zero clock(CAS latency of 1), one clock(CAS latency of 2)or
T0
RP(min)
Read
Read
Read
T1
from the PRECHARGE command.
Q0
T2
Q0
Q1
Rev.2
T3
Q1
Q0
Q2
T4
PRE
PRE
PRE
Q2
Q1
Q3
CMOS Synchronous Dynamic RAM
T5
t
RP
t
t
RP
RP
Q2
ACT
Q3
Hi-Z
T6
t
RP
ACT
Q3
Hi-Z
1,048,576 x 16 - Bit
T7
Page 24
Burst lengh= X
ACT
VG3617161ET
Hi-Z
T8