VG3617161ET-6 Powerchip, VG3617161ET-6 Datasheet - Page 17

• Manufacturer Part Number: VG3617161ET-6
• Description: 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
• Manufacturer: Powerchip

VIS
7.PRECHARGE
PRECHARGE
The t
cycle. The minimum number of clocks are calculated by dividing t
In the following table, minus means clocks before the reference, plus means time after the reference.
Document:1G5-0189
enters the idle state after t
burst is as followed.
CAS latency=
In order to write all data to the memory cell correctly, the asynchronous parameter”t
In summary, the PRECHARGE command can be asserted relative to the reference clock of the last valid data.
The PRECHARGE command can be asserted anytime after t
Soon after the PRECHARGE command is asserted, PRECHARGE operation is performed. The synchronous DRAM
The earliest timing in a READ cycle that a PRECHARGE command can be asserted without losing any data in the
DPL(
CAS latency
Command
CAS latency=2
DQ
CLK
Command
CAS latency=3
DQ
MIN
.)
2
3
specification defines the earliest time that a PRECHARGE command can be asserted after a WRITE
2: One clock earlier than the last output data.
3: Two clocks earlier than the last output data.
RP(min)
READ
-1
-2
is satisfied. The parameter t
T0
Read
Read
T1
+t
+t
WRITE
DPL(min.)
DPL(min)
T2
Rev.2
RP
Q0
DPL(min.)
RAS(min)
is the time required to perform the PRECHARGE.
T3
by the clock cycle time.
is satisfied.
Q0
Q1
CMOS Synchronous Dynamic RAM
T4
PRE
PRE
Q1
Q2
DPL
T5
” must be satisfied.
Q3
Q2
T6
1,048,576 x 16 - Bit
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Page 17
Q3
VG3617161ET
(t
RAS
T7
Burst lengh=4
is satisfied)
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