VG3617161ET-6 Powerchip, VG3617161ET-6 Datasheet - Page 20

• Manufacturer Part Number: VG3617161ET-6
• Description: 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
• Manufacturer: Powerchip

VIS
9.READ/WRITE Command Interval
READ to READ Command Interval
WRITE to WRITE Command Interval
Document:1G5-0189
9.1 READ to READ command interval
9.2 WRITE to WRITE Command Interval
Command
Command
even if the previous READ operation has not completed. READ will be interrupted by another READ.
CLK
DQ
and the new burst will begin with the new WRITE command. WRITE will be interrupted by another WRITE.
CLK
DQ
When a new READ command is asserted during a READ cycle, it will be effective after the CAS latency,
A READ command can be asserted in every clock without restriction.
When a new WRITE command is asserted during a WRITE cycle, the previous burst will be terminated
A WRITE command can be asserted in every clock without restriction.
T0
T0
Read A
Write A
QA0
1 cycle
1 cycle
T1
T1
Read B
Write B
QB0
T2
T2
QA0
QB1
Rev.2
T3
T3
QB0
QB2
T4
T4
QB1
CMOS Synchronous Dynamic RAM
QB3
T5
T5
QB2
Hi-Z_
T6
T6
Burst lengh=4, CAS latency=2
Burst lengh=4, CAS latency=2
QB3
1,048,576 x 16 - Bit
Page 20
T7
T7
VG3617161ET
Hi-Z_
T8
T8