VG3617161ET-6 Powerchip, VG3617161ET-6 Datasheet - Page 21

• Manufacturer Part Number: VG3617161ET-6
• Description: 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
• Manufacturer: Powerchip

VIS
WRITE to READ Command Interval
Document:1G5-0189
9.4 READ to WRITE Command Interval
9.3 WRITE to READ Command Interval
Command
CAS latency=2
DQ
Command
CAS latency=3
DQ
CLK
ceding the READ command will be written. The data bus must be in high-impedance at least one cycle prior
to the first D
using DQM before the WRITE command. DQM must be high at least 3 clocks prior to the WRITE command.
This restriction is necessary to avoid a data bus conflict.
During READ cycle, READ can be interrupted by WRITE. The data bus must be in high-impedance
The WRITE command to READ command interval is a minimum of 1 cycle. Only the WRITE data pre-
OUT
.
T0
WRITE A
Write A
DA0
DA0
1 cycle
T1
Read B
Read B
Hi-Z
Hi-Z
T2
Rev.2
T3
QB0
T4
CMOS Synchronous Dynamic RAM
QB1
QB0
T5
QB2
QB1
T6
1,048,576 x 16 - Bit
QB3
QB2
Page 21
T7
Burst lengh=4
VG3617161ET
QB3
T8