VG3617161ET-6 Powerchip, VG3617161ET-6 Datasheet - Page 12

• Manufacturer Part Number: VG3617161ET-6
• Description: 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
• Manufacturer: Powerchip

Note 1. H : Hight level, L : low level, X : High or low level(Don't care).
VIS
Current state
Self refresh
Self refresh
recovery
Power down
(PD)
Both banks
idle
Any state
other than
listed above
Document:1G5-0189
2.5 Command Truth Table for CKE
(SR)
2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied
3. Power down and Self refresh can be entered only from the both banks idle state.
4. Must be legal command as defined in Operative Command Table.
5 .IIIegal if t
before any command other than EXIT.
SRX
CKE
is not satisfied.
n-1
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
RAS
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
n
L
L
L
L
L
L
L
L
L
L
L
L
L
L
CS
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS
H
H
H
H
H
H
H
H
X
X
L
X
X
L
X
L
X
X
X
X
X
X
L
L
L
X
L
L
L
X
X
X
X
X
CAS
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
WE
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
Rev.2
Address
Code
Code
Op-
Op-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID,CLK(n-1)would exit S.R.
SR Recovery
SR Recovery
ILLEGAL
ILLEGAL
Maintain S.R.
Idle after t
Idle after t
ILLEGAL
ILLEGAL
Begin clock suspend next cycle
Begin clock suspend next cycle
ILLEGAL
ILLEGAL
Exit clock suspend next cycle
Maintain clock suspend
INVALID, CLK(n-1) would exit P.D.
EXIT
Maintain power down mode
Refer to operations in Operative
Command Table
Refer to operations in Operative
Command Table
Refer to operation in Operative
Command Table
Refresh
Refer to operations in Operative
Command Table
Refer to operations in Operative
Command Table
Refer to operations in Operative
Command Table
Refer to operations in Operative
Command Table
Self refresh
Refer to operations in Operative
Command Table
Power down
Refer to operations in Operative
Command Table
Begin clock suspend next cycle
Exit clock suspend next cycle
Maintain clock suspend
CMOS Synchronous Dynamic RAM
PD
RC
RC

Idle
Action
1,048,576 x 16 - Bit
Page 12
VG3617161ET
2
2
2
2
5
5
2
2
3
3
4
Notes