LM3S1607 Luminary Micro, Inc, LM3S1607 Datasheet - Page 132

• Manufacturer Part Number: LM3S1607
• Description: Lm3s1607 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Hibernation Module
7.4
Table 7-1. Hibernation Module Register Map
132
0x030-
Offset
0x00C
0x01C
0x12C
0x000
0x004
0x008
0x010
0x014
0x018
0x020
0x024
Name
HIBRTCC
HIBRTCM0
HIBRTCM1
HIBRTCLD
HIBCTL
HIBIM
HIBRIS
HIBMIS
HIBIC
HIBRTCT
HIBDATA
■
■
■
Register Map
Table 7-1 on page 132 lists the Hibernation registers. All addresses given are relative to the Hibernation
Module base address at 0x400F.C000.
Note:
When the hibernation module has no externally applied voltage and detects a change to either
VDD or VBAT, it resets all hibernation module registers to the value in Table 7-1 on page 132.
Reset During Hibernation Module Disable
When the module has either not been enabled or has been disabled by software, the reset is
passed through to the Hibernation module circuitry and the internal state of the module is reset.
Reset While HIB Module is in Hibernation Mode
While in Hibernation mode, or while transitioning from Hibernation mode to run mode (leaving
the power cut), the reset generated by the POR circuitry of the device is suppressed, and the
state of the Hibernation module's registers is unaffected.
Reset While HIB Module is in Normal Mode
While in normal mode (not hibernating), any reset is suppressed, and the content/state of the
control and data registers is unaffected.
Software must initialize any control or data registers in this condition. Therefore, software is the
only mechanism to enable or disable the oscillator and real-time clock operation, or to clear
contents of the data memory. The only state that must be cleared by a reset operation while not
in Hibernation mode is any state that prevents software from managing the interface.
HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and require a delay of t
accesses. See “Register Access Timing” on page 125.
R/W1C
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
0xFFFF.FFFF
0xFFFF.FFFF
0xFFFF.FFFF
0x0000.7FFF
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
Reset
Preliminary
Description
Hibernation RTC Counter
Hibernation RTC Match 0
Hibernation RTC Match 1
Hibernation RTC Load
Hibernation Control
Hibernation Interrupt Mask
Hibernation Raw Interrupt Status
Hibernation Masked Interrupt Status
Hibernation Interrupt Clear
Hibernation RTC Trim
Hibernation Data
HIB_REG_WRITE
between write
June 02, 2008
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