LM3S1607 Luminary Micro, Inc, LM3S1607 Datasheet - Page 193

• Manufacturer Part Number: LM3S1607
• Description: Lm3s1607 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

9.3.3.3
9.3.4
9.3.4.1
June 02, 2008
Table 9-10. Channel Control Word Configuration for Peripheral Transmit Example
Note:
Start the Transfer
Now the channel is configured and is ready to start.
1.
The μDMA controller is now configured for transfer on channel 7. The controller will make transfers
to the peripheral whenever the peripheral asserts a DMA request. The transfers will continue until
the entire buffer of 64 bytes has been transferred. When that happens, the μDMA controller will
disable the channel and set the XFERMODE field of the channel control word to 0 (Stopped). The
status of the transfer can be checked by reading bit 7 of the DMA Channel Enable Set
(DMAENASET) register. This bit will be automatically cleared when the transfer is complete. The
status can also be checked by reading the XFERMODE field of the channel control word at offset
0x078. This field will automatically be set to 0 at the end of the transfer.
If peripheral interrupts were enabled, then the peripheral interrupt handler would receive an interrupt
when the entire transfer was complete.
Configuring a Peripheral for Ping-Pong Receive
This example will set up the μDMA controller to continuously receive 8-bit data from a peripheral
into a pair of 64 byte buffers. The peripheral has a receive FIFO with a trigger level of 8. The example
peripheral will use μDMA channel 8.
Configure the Channel Attributes
First, configure the channel attributes:
1.
Field in DMACHCTL
DSTINC
DSTSIZE
SRCINC
SRCSIZE
reserved
ARBSIZE
XFERSIZE
NXTUSEBURST
XFERMODE
Enable the channel by setting bit 7 of the DMA Channel Enable Set (DMAENASET) register.
Set bit 7 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority Clear
(DMAPRIOCLR) registers to set the channel to High priority or Default priority.
In this example, it is not important if the peripheral makes a single request or a burst request.
Since the peripheral has a FIFO that will trigger at a level of 4, the arbitration size is set to
4. If the peripheral does make a burst request, then 4 bytes will be transferred, which is
what the FIFO can accomodate. If the peripheral makes a single request (if there is any
space in the FIFO), then one byte will be transferred at a time. If it is important to the
application that transfers only be made in bursts, then the channel useburst SET[n] bit
should be set by writing a 1 to bit 7 of the DMA Channel Useburst Set
(DMAUSEBURSTSET) register.
Preliminary
31:30
29:28
27:26
25:24
23:18
17:14
Bits
13:4
2:0
3
Value
63
3
0
0
0
0
2
0
1
Description
Destination address does not increment
8-bit destination data size
8-bit source address increment
8-bit source data size
Reserved
Arbitrates after 4 transfers
Transfer 64 items
N/A for this transfer type
Use Basic transfer mode
LM3S1607 Microcontroller
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