LM3S1607 Luminary Micro, Inc, LM3S1607 Datasheet - Page 14

• Manufacturer Part Number: LM3S1607
• Description: Lm3s1607 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
Register 10:
Register 11:
Internal Memory ........................................................................................................................... 147
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Register 2:
Register 3:
Register 4:
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Register 8:
Register 9:
Register 10:
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Register 14:
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Register 19:
Register 20:
Register 21:
Register 22:
Micro Direct Memory Access (μDMA) ........................................................................................ 176
Register 1:
Register 2:
Register 3:
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Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
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Register 20:
Register 21:
Register 22:
14
Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 145
Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 146
ROM Control (RMCTL), offset 0x0F0 .............................................................................. 153
Flash Memory Address (FMA), offset 0x000 .................................................................... 154
Flash Memory Data (FMD), offset 0x004 ......................................................................... 155
Flash Memory Control (FMC), offset 0x008 ..................................................................... 156
Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 158
Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 159
Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 160
USec Reload (USECRL), offset 0x140 ............................................................................ 161
ROM Version Register (RMVER), offset 0x0F4 ................................................................ 162
Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 163
Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 164
User Debug (USER_DBG), offset 0x1D0 ......................................................................... 165
User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 166
User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 167
User Register 2 (USER_REG2), offset 0x1E8 .................................................................. 168
User Register 3 (USER_REG3), offset 0x1EC ................................................................. 169
Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 170
Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 171
Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 172
Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 173
Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 174
Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 175
DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ...................... 198
DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................ 199
DMA Channel Control Word (DMACHCTL), offset 0x008 .................................................. 200
DMA Status (DMASTAT), offset 0x000 ............................................................................ 204
DMA Configuration (DMACFG), offset 0x004 ................................................................... 206
DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 .................................. 207
DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C .................... 208
DMA Channel Wait on Request Status (DMAWAITSTAT), offset 0x010 ............................. 209
DMA Channel Software Request (DMASWREQ), offset 0x014 ......................................... 210
DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 .................................... 211
DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C ................................. 213
DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 .............................. 214
DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 216
DMA Channel Enable Set (DMAENASET), offset 0x028 ................................................... 217
DMA Channel Enable Clear (DMAENACLR), offset 0x02C ............................................... 219
DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 .................................... 220
DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................. 222
DMA Channel Priority Set (DMAPRIOSET), offset 0x038 ................................................. 223
DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C .............................................. 225
DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................ 226
DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ......................................... 228
DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 ......................................... 229
Preliminary
June 02, 2008