LM3S1607 Luminary Micro, Inc, LM3S1607 Datasheet - Page 66

• Manufacturer Part Number: LM3S1607
• Description: Lm3s1607 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

System Control
6.1.5.3
6.1.5.4
6.1.5.5
66
Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the
design, the XTAL field value is internally translated to the PLL settings.
Main PLL Frequency Configuration
The main PLL is disabled by default during power-on reset and is enabled later by software if
required. Software specifies the output divisor to set the system clock frequency, and enables the
main PLL to drive the output.
If the main oscillator provides the clock reference to the main PLL, the translation provided by
hardware and used to program the PLL is available for software in the XTAL to PLL Translation
(PLLCFG) register (see page 83). The internal translation provides a translation within ± 1% of the
targeted PLL VCO frequency.
The Crystal Value field (XTAL) on page 79 describes the available crystal choices and default
programming of the PLLCFG register. The crystal number is written into the XTAL field of the
Run-Mode Clock Configuration (RCC) register. Any time the XTAL field changes, the new settings
are translated and the internal PLL settings are updated.
PLL Modes
The PLL hastwo modes of operation: Normal and Power-Down
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■
The modes are programmed using the RCC/RCC2 register fields (see page 79 and page 85).
PLL Operation
If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
to the new setting. The time between the configuration change and relock is T
20-7 on page 503). During the relock time, the affected PLL is not usable as a clock reference.
The PLL is changed by one of the following:
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■
A counter is defined to measure the T
oscillator. The range of the main oscillator has been taken into account and the down counter is set
to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). When the XTAL value is
greater than 0x0f, the down counter is set to 0x2400 to maintain the required lock time on higher
frequency crystal inputs. Hardware is provided to keep the PLL from being used as a system clock
until the T
to have a stable clock source (like the main oscillator) before the RCC/RCC2 register is switched
to use the PLL.
If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system
control hardware continues to clock the controller from the oscillator selected by the RCC/RCC2
register until the main PLL is stable (T
can use many methods to ensure that the system is clocked from the main PLL, including periodically
polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the PLL Lock
interrupt.
Normal: The PLL multiplies the input clock reference and drives the output.
Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.
Change to the XTAL value in the RCC register—writes of the same value do not cause a relock.
Change in the PLL from Power-Down to Normal mode.
READY
condition is met after one of the two changes above. It is the user's responsibility
Preliminary
READY
READY
requirement. The counter is clocked by the main
time met), after which it changes to the PLL. Software
READY
(see Table
June 02, 2008