IDT72V3673L10PF IDT, Integrated Device Technology Inc, IDT72V3673L10PF Datasheet - Page 13

• Manufacturer Part Number: IDT72V3673L10PF
• Description: IC SYNCFIFO 8192X36 10NS 128TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3673L10PF

• Function: Asynchronous, Synchronous
• Memory Size: 288K (8K x 36)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3673L10PF

synchronized to CLKB. Table 4 shows the relationship of each port flag to the
number of words stored in memory.
EMPTY/OUTPUT READY FLAGS (EF/OR)
(OR) function is selected. When the Output-Ready flag is HIGH, new data is
present in the FIFO output register. When the Output Ready flag is LOW, the
previous data word is present in the FIFO output register and attempted FIFO
reads are ignored.
the Empty Flag is HIGH, data is available in the FIFO’s memory for reading to
the output register. When the Empty Flag is LOW, the previous data word is
present in the FIFO output register and attempted FIFO reads are ignored.
that reads data from its array (CLKB). For both the FWFT and IDT Standard
modes, the FIFO read pointer is incremented each time a new word is clocked
to its output register. The state machine that controls an Output Ready flag
monitors a write pointer and read pointer comparator that indicates when the
FIFO memory status is empty, empty+1, or empty+2.
to the FIFO output register in a minimum of three cycles of the Output Ready flag
synchronizing clock. Therefore, an Output Ready flag is LOW if a word in memory
is the next data to be sent to the FlFO output register and three cycles of the port
Clock that reads data from the FIFO have not elapsed since the time the word
was written. The Output Ready flag of the FIFO remains LOW until the third LOW-
to-HIGH transition of the synchronizing clock occurs, simultaneously forcing the
Output Ready flag HIGH and shifting the word to the FIFO output register.
Flag will indicate the presence of data available for reading in a minimum of two
cycles of the Empty Flag synchronizing clock. Therefore, an Empty Flag is LOW
if a word in memory is the next data to be sent to the FlFO output register and
two cycles of the port Clock that reads data from the FIFO have not elapsed since
the time the word was written. The Empty Flag of the FIFO remains LOW until
the second LOW-to-HIGH transition of the synchronizing clock occurs, forcing
the Empty Flag HIGH; only then can data be read.
clock begins the first synchronization cycle of a write if the clock transition occurs
at time t
can be the first synchronization cycle (see Figures 11 and 12).
FULL/INPUT READY FLAGS (FF/IR)
is selected. In IDT Standard mode, the Full Flag (FF) function is selected. For
both timing modes, when the Full/Input Ready flag is HIGH, a memory location
is free in the FIFO to receive new data. No memory locations are free when
the Full/Input Ready flag is LOW and attempted writes to the FIFO are ignored.
writes data to its array (CLKA). For both FWFT and IDT Standard modes, each
time a word is written to a FIFO, its write pointer is incremented. The state machine
that controls a Full/Input Ready flag monitors a write pointer and read pointer
comparator that indicates when the FlFO memory status is full, full-1, or full-2.
From the time a word is read from a FIFO, its previous memory location is ready
to be written to in a minimum of two cycles of the Full/Input Ready flag
synchronizing clock. Therefore, an Full/Input Ready flag is LOW if less than two
cycles of the Full/Input Ready flag synchronizing clock have elapsed since the
next memory write location has been read. The second LOW-to-HIGH transition
on the Full/Input Ready flag synchronizing clock after the read sets the Full/Input
Ready flag HIGH.
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
These are dual purpose flags. In the FWFT mode, the Output Ready
In the IDT Standard mode, the Empty Flag (EF) function is selected. When
The Empty/Output Ready flag of a FIFO is synchronized to the port clock
In FWFT mode, from the time a word is written to a FIFO, it can be shifted
In IDT Standard mode, from the time a word is written to a FIFO, the Empty
A LOW-to-HIGH transition on an Empty/Output Ready flag synchronizing
This is a dual purpose flag. In FWFT mode, the Input Ready (IR) function
The Full/Input Ready flag of a FlFO is synchronized to the port clock that
SKEW1
or greater after the write. Otherwise, the subsequent clock cycle
TM
WITH
13
begins the first synchronization cycle of a read if the clock transition occurs at
time t
can be the first synchronization cycle (see Figures 13 and 14).
ALMOST-EMPTY FLAG (AE)
reads data from its array (CLKB). The state machine that controls an Almost-
Empty flag monitors a write pointer and read pointer comparator that indicates
when the FIFO memory status is almost-empty, almost-empty+1, or almost-
empty+2. The Almost-Empty state is defined by the contents of register X. These
registers are loaded with preset values during a FIFO reset, programmed from
Port A, or programmed serially (see Almost-Empty flag and Almost-Full flag
offset programming section). An Almost-Empty flag is LOW when its FIFO
contains X or less words and is HIGH when its FIFO contains (X+1) or more
words. Note that a data word present in the FIFO output register has been read
from memory.
clock are required after a FIFO write for its Almost-Empty flag to reflect the new
level of fill. Therefore, the Almost-Empty flag of a FIFO containing (X+1) or more
words remains LOW if two cycles of its synchronizing clock have not elapsed
since the write that filled the memory to the (X+1) level. An Almost-Empty flag
is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock
after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH
transition of an Almost-Empty flag synchronizing clock begins the first synchro-
nization cycle if it occurs at time t
to (X+1) words. Otherwise, the subsequent synchronizing clock cycle may be
the first synchronization cycle. (See Figure 15).
ALMOST-FULL FLAG (AF)
data to its array. The state machine that controls an Almost-Full flag monitors
a write pointer and read pointer comparator that indicates when the FIFO
memory status is almost-full, almost-full-1, or almost-full-2. The Almost-Full state
is defined by the contents of register Y. These registers are loaded with preset
values during a FlFO reset or, programmed from Port A, or programmed
serially (see Almost-Empty flag and Almost-Full flag offset programming
section). An Almost-Full flag is LOW when the number of words in its FIFO is
greater than or equal to (2,048-Y), (4,096-Y), or (8,192-Y) for the IDT72V3653,
IDT72V3663, or IDT72V3673 respectively. An Almost-Full flag is HIGH when
the number of words in its FIFO is less than or equal to [2,048-(Y+1)],
[4,096-(Y+1)], or [8,192-(Y+1)] for the IDT72V3653, IDT72V3663, or
IDT72V3673 respectively. Note that a data word present in the FIFO output
register has been read from memory.
are required after a FIFO read for its Almost-Full flag to reflect the new level
of fill. Therefore, the Almost-Full flag of a FIFO containing [2,048/4,096/8,192-
(Y+1)] or less words remains LOW if two cycles of its synchronizing clock have
not elapsed since the read that reduced the number of words in memory to
[2,048/4,096/8,192-(Y+1)]. An Almost-Full flag is set HIGH by the second
LOW-to-HIGH transition of its synchronizing clock after the FIFO read that
reduces the number of words in memory to [2,048/4,096/8,192-(Y+1)]. A
LOW-to-HIGH transition of an Almost-Full flag synchronizing clock begins the
first synchronization cycle if it occurs at time t
reduces the number of words in memory to [2,048/4,096/8,192-(Y+1)].
Otherwise, the subsequent synchronizing clock cycle may be the first synchro-
nization cycle (see Figure 16).
A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock
The Almost-Empty flag of a FIFO is synchronized to the port clock that
Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing
The Almost-Full flag of a FIFO is synchronized to the port clock that writes
Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock
SKEW
1
or greater after the read. Otherwise, the subsequent clock cycle
COMMERCIAL TEMPERATURE RANGE
SKEW2
or greater after the write that fills the FIFO
SKEW2
or greater after the read that