IDT72V3673L10PF IDT, Integrated Device Technology Inc, IDT72V3673L10PF Datasheet - Page 4

• Manufacturer Part Number: IDT72V3673L10PF
• Description: IC SYNCFIFO 8192X36 10NS 128TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3673L10PF

• Function: Asynchronous, Synchronous
• Memory Size: 288K (8K x 36)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3673L10PF

PIN DESCRIPTIONS
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
Symbol
A0-A35
AE
AF
B0-B35
BE/FWFT
BM
CLKA
CLKB
CSA
CSB
EF/OR
ENA
ENB
FF/IR
FS0/SD
FS1/SEN
FS2
(1)
(1)
Almost-Empty Flag
(Port B)
Almost-Full Flag
(Port A)
Big-Endian/
First Word
Fall Through
Bus-Match Select
(Port B)
Port A Clock
Port B Clock
Port A Chip
Select
Port B Chip
Select
Empty/Output
Ready Flag
(Port B)
Port A Enable
Port B Enable
Full/Input
Ready Flag
(Port A)
Flag Offset Select 0/
Serial Data,
Flag Offset Select 1/
Serial Enable
Flag Offset Select 2
Port A Data
Port B Data
Name
I/O
I/O
I/O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
36-bit bidirectional data port for side A.
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty
locations in the FIFO is less than or equal to the value in the Almost-Full A offset register, Y.
36-bit bidirectional data port for side B.
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-Endian operation.
from Port B first. A LOW on BE will select Little-Endian operation. In this case, the least significant
byte or word written to Port A is read from Port B first. After Master Reset, this pin selects the timing
mode. A HIGH on FWFT selects IDT Standard mode, a LOW selects First Word Fall Through
mode. Once the timing mode has been selected, the level on FWFT must be static throughout
device operation.
A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of
SIZE. A LOW selects long word operation. BM works with SIZE and BE to select the bus size and
endian arrangement for Port B. The level of BM must be static throughout device operation.
CLKA is a continuous clock that synchronizes all data transfers through Port A and can be
asynchronous or coincident to CLKB. FF/IR and AF are synchronized to the LOW-to-HIGH
transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through Port B and can be
asynchronous or coincident to CLKA. EF/OR and AE are synchronized to the LOW-to-HIGH
transition of CLKB.
CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A. The
A0-A35 outputs are in the high-impedance state when CSA is HIGH.
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B.
The B0-B35 outputs are in the high-impedance state when CSB is HIGH.
This is a dual function pin. In the IDT Standard mode, the EF function is selected. EF indicates
whether or not the FIFO memory is empty. In the FWFT mode, the OR function is selected. OR indicates
the presence of valid data on the B0-B35 outputs, available for reading. EF/OR is synchronized to the
LOW-to-HIGH transition of CLKB.
This is a dual function pin. In the IDT Standard mode, the FF function is selected. FF indicates
indicates whether or not there is space available for writing to the FIFO memory. FF/IR is
synchronized to the LOW-to-HIGH transition of CLKA.
FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During
Three offset register programming methods are available: automatically load one of five preset
values (8, 16, 64, 256 or 1,024), parallel load from Port A, and serial load.
synchronous to the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on
CLKA load the bit present on FS0/SD into the X and Y registers. The number of bit writes required
to program the offset registers is 22 for the 72V3653, 24 for the 72V3663, and 26 for the 72V3673.
The first bit write stores the Y-register MSB and the last bit write stores the X-register LSB.
In this case, depending on the bus size, the most significant byte or word written to Port A is read
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B.
whether or not the FIFO memory is full. In the FWFT mode, the IR function is selected. IR
Reset, FS1/SEN and FS0/SD, together with FS2 select the flag offset programming method.
When serial load is selected for flag offset register programming, FS1/SEN is used as an enable
the FIFO is less than or equal to the value in the Almost-Empty B offset register, X.
TM
WITH
4
Description
COMMERCIAL TEMPERATURE RANGE