IDT72V3673L10PF IDT, Integrated Device Technology Inc, IDT72V3673L10PF Datasheet - Page 24

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IDT72V3673L10PF

Manufacturer Part Number
IDT72V3673L10PF
Description
IC SYNCFIFO 8192X36 10NS 128TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet

Specifications of IDT72V3673L10PF

Function
Asynchronous, Synchronous
Memory Size
288K (8K x 36)
Data Rate
100MHz
Access Time
10ns
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V3673L10PF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72V3673L10PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V3673L10PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. t
2. If Port B size is word or byte, t
NOTES:
1. t
2. FIFO Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been read from the FIFO.
3. If Port B size is word or byte, AE is set LOW by the last word or byte read from the FIFO, respectively.
CLKB
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
CLKA
A0-A35
B0-B35
ENA
ENB
CLKA edge is less than t
CLKB edge is less than t
SKEW1
SKEW2
CLKA
W/RA
CLKB
W/RB
AE
MBB
CSA
MBA
CSB
ENA
ENB
EF
FF
is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
LOW
HIGH
LOW
HIGH
FIFO Full
LOW
HIGH
Previous Word in FIFO Output Register
t
CLKH
X Words in FIFO
t
ENS2
SKEW1
SKEW2
t
CLK
Figure 15. Timing for AE
Figure 14. FF FF FF FF FF Flag Timing and First Available Write when FIFO is Full (IDT Standard Mode)
t
SKEW1
ENS2
, then FF may transition HIGH one CLKA cycle later than shown.
, then AE may transition HIGH one CLKB cycle later than shown.
t
CLKL
is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.
t
t
SKEW2
ENH
t
SKEW1
t
t
ENH
(1)
A
AE
AE
AE
AE when the FIFO is Almost-Empty (IDT Standard and FWFT Modes).
(1)
1
TM
WITH
1
t
CLKH
t
CLK
24
t
CLKL
2
t
PAE
2
Next Word From FIFO
t
WFF
(X+1) Words in FIFO
t
t
ENS2
ENS2
t
DS
COMMERCIAL TEMPERATURE RANGE
To FIFO
t
ENS2
t
t
t
WFF
ENH
t
DH
ENH
t
t
ENH
PAE
4662 drw16
4662 drw 17

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