IDT72V3673L10PF IDT, Integrated Device Technology Inc, IDT72V3673L10PF Datasheet - Page 28

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IDT72V3673L10PF

Manufacturer Part Number
IDT72V3673L10PF
Description
IC SYNCFIFO 8192X36 10NS 128TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet

Specifications of IDT72V3673L10PF

Function
Asynchronous, Synchronous
Memory Size
288K (8K x 36)
Data Rate
100MHz
Access Time
10ns
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V3673L10PF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72V3673L10PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V3673L10PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
NOTES:
1. Mailbox feature is not supported in depth expansion applications. (MBA + MBB tie to GND)
2. Transfer clock should be set either to the Write Port Clock (CLKA) or the Read Port Clock (CLKB), whichever is faster.
3. The amount of time it takes for EF/OR of the last FIFO in the chain to go HIGH (i.e. valid data to appear on the last FIFO’s outputs) after a word has been written to the first FIFO is the
4. The amount of time it takes for FF/IR of the first FIFO in the chain to go HIGH after a word has been read from the last FIFO is the sum of the delays for each individual FIFO:
V
CC
sum of the delays for each individual FIFO: (N - 1)*(4*transfer clock) + 3*T
(N - 1)*(3*transfer clock) + 2*T
DATA IN (Dn)
WRITE
ALMOST-FULL FLAG (AF)
WRITE SELECT (W/RA)
WRITE CLOCK (CLKA)
WRITE ENABLE (ENA)
FULL FLAG/
INPUT READY (FF/IR)
CHIP SELECT (CSA)
A
0
-A
35
n
Figure 21. Block Diagram of 256 x 36, 512 x 36, 1,024 x 36 Synchronous FIFO Memory with
MBA
WCLK
, where N is the number of FIFOs in the expansion and T
Programmable Flags used in Depth Expansion Configuration
72V3653
72V3663
72V3673
IDT
TM
WITH
CSB
CLKB
EF/OR
ENB
B
Qn
W/RB
MBB
0
-B
RCLK
35
TRANSFER CLOCK
, where N is the number of FIFOs in the expansion and T
V
CC
28
n
V
CC
A
CLKA
W/RA
0
WCLK
FF/IR
MBA
ENA
CSA
-A
Dn
35
is the CLKA period.
72V3653
72V3663
72V3673
IDT
COMMERCIAL TEMPERATURE RANGE
RCLK
is the CLKB period.
EMPTY FLAG/
OUTPUT READY (EF/OR)
MBB
READ CLOCK (CLKB)
CHIP SELECT (CSB)
READ ENABLE (ENB)
READ SELECT (W/RB)
ALMOST-EMPTY FLAG (AE)
n
B
DATA OUT (Qn)
0
-B
35
READ
4662 drw23
V
CC

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