IDT72V3673L10PF IDT, Integrated Device Technology Inc, IDT72V3673L10PF Datasheet - Page 14

• Manufacturer Part Number: IDT72V3673L10PF
• Description: IC SYNCFIFO 8192X36 10NS 128TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3673L10PF

• Function: Asynchronous, Synchronous
• Memory Size: 288K (8K x 36)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3673L10PF

MAILBOX REGISTERS
to pass command and control information between Port A and Port B without
putting it in queue. The Mailbox select (MBA, MBB) inputs choose between a
mail register and a FIFO for a port data transfer operation. The usable width
of both the Mail1 and Mail2 Registers matches the selected bus size for Port B.
a Port A write is selected by CSA, W/RA, and ENA with MBA HIGH. If the
selected Port B bus size is 36 bits, the usable width of the Mail1 Register employs
data lines A0-A35. If the selected Port B bus size is 18 bits, then the usable width
of the Mail1 Register employs data lines A0-A17. (In this case, A18-A35 are
don’t care inputs.) If the selected Port B bus size is 9 bits, then the usable width
of the Mail1 Register employs data lines A0-A8. (In this case, A9-A35 are don’t
care inputs.)
Register when a Port B write is selected by CSB, W/RB, and ENB with MBB
HIGH. If the selected Port B bus size is 36 bits, the usable width of the Mail2
employs data lines B0-B35. If the selected Port B bus size is 18 bits, then the
usable width of the Mail2 Register employs data lines B0-B17. (In this case, B18-
B35 are don’t care inputs.) If the selected Port B bus size is 9 bits, then the usable
width of the Mail2 Register employs data lines B0-B8. (In this case, B9-B35 are
don’t care inputs.)
MBF2) LOW. Attempted writes to a mail register are ignored while the mail flag
is LOW.
the FIFO output register when the port Mailbox select input is LOW and from
the mail register when the port Mailbox select input is HIGH.
transition on CLKB when a Port B read is selected by CSB, W/RB, and ENB
with MBB HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on
B0-B35. For an 18-bit bus size, 18 bits of mailbox data are placed on B0-B17.
(In this case, B18-B35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox
data are placed on B0-B8. (In this case, B9-B35 are indeterminate.)
transition on CLKA when a Port A read is selected by CSA, W/RA, and ENA
with MBA HIGH.
an 18-bit bus size, 18 bits of mailbox data are placed on A0-A17. (In this case,
A18-A35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are
placed on A0-A8. (In this case, A9-A35 are indeterminate.)
when new data is written to the register. The Endian select feature has no effect
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
Two 36-bit bypass registers are on the IDT72V3653/72V3663/72V3673
A LOW-to-HIGH transition on CLKA writes data to the Mail1 Register when
A LOW-to-HIGH transition on CLKB writes B0-B35 data to the Mail2
Writing data to a mail register sets its corresponding flag (MBF1 or
When data outputs of a port are active, the data on the bus comes from
The Mail1 Register Flag (MBF1) is set HIGH by a LOW-to-HIGH
The Mail2 Register Flag (MBF2) is set HIGH by a LOW-to-HIGH
For a 36-bit bus size, 36 bits of mailbox data are placed on A0-A35. For
The data in a mail register remains intact after it is read and changes only
TM
WITH
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on mailbox data. For mail register and mail register flag timing diagrams, see
Figure 17 and 18.
BUS SIZING
9-bit byte format for data read from the FIFO. The levels applied to the Port B
Bus Size select (SIZE) and the Bus-Match select (BM) determine the Port B bus
size. These levels should be static throughout FIFO operation. Both bus size
selections are implemented at the completion of Reset, by the time the Full/Input
Ready flag is set HIGH, as shown in Figure 2.
B when the bus size selection is either byte-or word-size. They are referred
to as Big-Endian (most significant byte first) and Little-Endian (least significant
byte first). The level applied to the Big-Endian select (BE) input during the LOW-
to-HIGH transition of RS1 selects the endian method that will be active during
FIFO operation. BE is a don’t care input when the bus size selected for Port
B is long word. The endian method is implemented at the completion of Reset,
by the time the Full/Input Ready flag is set HIGH, as shown in Figure 2.
the IDT72V3653/72V3663/72V3673. Bus-matching operations are done after
data is read from the FIFO RAM. These bus-matching operations are not
available when transferring data via mailbox registers. Furthermore, both the
word- and byte-size bus selections limit the width of the data bus that can be used
for mail register operations. In this case, only those byte lanes belonging to the
selected word- or byte-size bus can carry mailbox data. The remaining data
outputs will be indeterminate. The remaining data inputs will be don’t care inputs.
For example, when a word-size bus is selected, then mailbox data can be
transmitted only between A0-A17 and B0-B17. When a byte-size bus is
selected, then mailbox data can be transmitted only between A0-A8 and B0-
B8. (See Figures 17 and 18).
BUS-MATCHING FIFO READS
word bus size is implemented, the entire long word immediately shifts to the FIFO
output register. If byte or word size is implemented on Port B, only the first one
or two bytes appear on the selected portion of the FIFO output register, with the
rest of the long word stored in auxiliary registers. In this case, subsequent FIFO
reads output the rest of the long word to the FIFO output register in the order
shown by Figure 2.
outputs are indeterminate.
Data is read from the FIFO RAM in 36-bit long word increments. If a long
When reading data from FIFO in byte or word format, the unused B0-B35
The Port B bus can be configured in a 36-bit long word, 18-bit word, or
Two different methods for sequencing data transfer are available for Port
Only 36-bit long word data is written to or read from the FIFO memory on
COMMERCIAL TEMPERATURE RANGE