LM3S5632 Luminary Micro, Inc, LM3S5632 Datasheet - Page 28

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LM3S5632

Manufacturer Part Number
LM3S5632
Description
Lm3s5632 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet

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Architectural Overview
28
ARM FiRM-compliant Watchdog Timer
Controller Area Network (CAN)
Synchronous Serial Interface (SSI)
UART
16-bit PWM mode
32-bit down counter with a programmable load register
Separate watchdog clock with an enable
Programmable interrupt generation logic with interrupt masking
Lock register protection from runaway software
Reset generation logic with an enable/disable
User-enabled stalling when the controller asserts the CPU Halt flag during debug
Supports CAN protocol version 2.0 part A/B
Bit rates up to 1Mb/s
32 message objects, each with its own identifier mask
Maskable interrupt
Disable automatic retransmission mode for TTCAN
Programmable loop-back mode for self-test operation
Master or slave operation
Programmable clock bit rate and prescale
Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
Programmable data frame size from 4 to 16 bits
Internal loopback test mode for diagnostic/debug testing
Direct memory access (DMA)
Two fully programmable 16C550-type UARTs with IrDA support
Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service
loading
Programmable baud-rate generator allowing speeds up to 3.125 Mbps
Simple PWM mode with software-programmable output inversion of the PWM signal
Preliminary
June 02, 2008

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