LM3S5632 Luminary Micro, Inc, LM3S5632 Datasheet - Page 592

• Manufacturer Part Number: LM3S5632
• Description: Lm3s5632 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Univeral Serial Bus (USB) Controller
592
Bit/Field
4
3
2
1
0
DATAERR
RXRDY
FLUSH
OVER
Name
FULL
R/W0C
R/W0C
Type
W1S
RO
RO
Reset
0
0
0
0
0
Preliminary
Description
Flush FIFO
The CPU writes a 1 to this bit to flush the next packet to be read from
the endpoint receive FIFO. The FIFO pointer is reset and the RXRDY bit
is cleared.
Note:
Data Error
This bit is set when RXRDY is set if the data packet has a CRC or bit-stuff
error. It is cleared when RXRDY is cleared.
Note:
Overrun
This bit is set if an OUT packet cannot be loaded into the receive FIFO.
The CPU should clear this bit.
Note:
FIFO Full
This bit is set when no more packets can be loaded into the receive
FIFO.
Receive Packet Ready
This bit is set when a data packet has been received. The CPU should
clear this bit when the packet has been unloaded from the receive FIFO.
An interrupt is generated when the bit is set.
The FLUSH bit should only be used when RXRDY is set. At
other times, it may cause data to be corrupted. Also note that,
if the FIFO is double-buffered, FLUSH may need to be set
twice to completely clear the FIFO.
This bit is only valid when the endpoint is operating in ISO
mode. In Bulk mode, it always returns zero.
This bit is only valid when the endpoint is operating in ISO
mode. In Bulk mode, it always returns zero.
June 02, 2008