LM3S5632 Luminary Micro, Inc, LM3S5632 Datasheet - Page 6
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LM3S5632
Manufacturer Part Number
LM3S5632
Description
Lm3s5632 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S5632.pdf
(685 pages)
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Table of Contents
13.2.1 Sample Sequencers ................................................................................................................ 341
13.2.2 Module Control ........................................................................................................................ 342
13.2.3 Hardware Sample Averaging Circuit ......................................................................................... 343
13.2.4 Analog-to-Digital Converter ...................................................................................................... 343
13.2.5 Differential Sampling ............................................................................................................... 343
13.2.6 Internal Temperature Sensor .................................................................................................... 345
13.3
13.3.1 Module Initialization ................................................................................................................. 346
13.3.2 Sample Sequencer Configuration ............................................................................................. 346
13.4
13.5
14
14.1
14.2
14.2.1 Transmit/Receive Logic ........................................................................................................... 373
14.2.2 Baud-Rate Generation ............................................................................................................. 374
14.2.3 Data Transmission .................................................................................................................. 374
14.2.4 Serial IR (SIR) ......................................................................................................................... 375
14.2.5 FIFO Operation ....................................................................................................................... 376
14.2.6 Interrupts ................................................................................................................................ 376
14.2.7 Loopback Operation ................................................................................................................ 377
14.2.8 DMA Operation ....................................................................................................................... 377
14.2.9 IrDA SIR block ........................................................................................................................ 378
14.3
14.4
14.5
15
15.1
15.2
15.2.1 Bit Rate Generation ................................................................................................................. 416
15.2.2 FIFO Operation ....................................................................................................................... 416
15.2.3 Interrupts ................................................................................................................................ 416
15.2.4 Frame Formats ....................................................................................................................... 417
15.2.5 DMA Operation ....................................................................................................................... 424
15.3
15.4
15.5
16
16.1
16.2
16.2.1 I
16.2.2 Available Speed Modes ........................................................................................................... 457
16.2.3 Interrupts ................................................................................................................................ 458
16.2.4 Loopback Operation ................................................................................................................ 459
16.2.5 Command Sequence Flow Charts ............................................................................................ 459
16.3
16.4
6
Initialization and Configuration ................................................................................................. 345
Register Map .......................................................................................................................... 346
Register Descriptions .............................................................................................................. 347
Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 372
Block Diagram ........................................................................................................................ 373
Functional Description ............................................................................................................. 373
Initialization and Configuration ................................................................................................. 378
Register Map .......................................................................................................................... 379
Register Descriptions .............................................................................................................. 380
Synchronous Serial Interface (SSI) ................................................................................ 415
Block Diagram ........................................................................................................................ 415
Functional Description ............................................................................................................. 416
Initialization and Configuration ................................................................................................. 425
Register Map .......................................................................................................................... 426
Register Descriptions .............................................................................................................. 427
Inter-Integrated Circuit (I
Block Diagram ........................................................................................................................ 454
Functional Description ............................................................................................................. 454
Initialization and Configuration ................................................................................................. 465
I
2
2
C Bus Functional Overview .................................................................................................... 455
C Register Map ..................................................................................................................... 466
2
C) Interface ............................................................................ 454
Preliminary
June 02, 2008
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