LM3S310 Luminary Micro, Inc, LM3S310 Datasheet - Page 12

• Manufacturer Part Number: LM3S310
• Description: Lm3s310 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

List of Registers
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 196
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Synchronous Serial Interface (SSI) ............................................................................................. 232
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
12
Watchdog Interrupt Clear (WDTICR), offset 0x00C ................................................................ 179
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 ....................................................... 180
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014.................................................. 181
Watchdog Lock (WDTLOCK), offset 0xC00 ............................................................................ 182
Watchdog Test (WDTTEST), offset 0x418 .............................................................................. 183
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0..................................... 184
Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4..................................... 185
Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8..................................... 186
Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC .................................... 187
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ..................................... 188
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ..................................... 189
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ..................................... 190
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC .................................... 191
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0........................................ 192
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4........................................ 193
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8........................................ 194
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC ...................................... 195
UART Data (UARTDR), offset 0x000 ...................................................................................... 203
UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 .............................. 205
UART Flag (UARTFR), offset 0x018 ....................................................................................... 207
UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ................................................. 209
UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ........................................... 210
UART Line Control (UARTLCRH), offset 0x02C ..................................................................... 211
UART Control (UARTCTL), offset 0x030................................................................................. 213
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ................................................ 214
UART Interrupt Mask (UARTIM), offset 0x038 ........................................................................ 215
UART Raw Interrupt Status (UARTRIS), offset 0x03C............................................................ 217
UART Masked Interrupt Status (UARTMIS), offset 0x040 ...................................................... 218
UART Interrupt Clear (UARTICR), offset 0x044...................................................................... 219
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0.......................................... 220
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4.......................................... 221
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8.......................................... 222
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ......................................... 223
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0.......................................... 224
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4.......................................... 225
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8.......................................... 226
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ......................................... 227
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0............................................. 228
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4............................................. 229
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8............................................. 230
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ............................................ 231
SSI Control 0 (SSICR0), offset 0x000 ..................................................................................... 243
SSI Control 1 (SSICR1), offset 0x004 ..................................................................................... 245
SSI Data (SSIDR), offset 0x008 .............................................................................................. 247
SSI Status (SSISR), offset 0x00C ........................................................................................... 248
SSI Clock Prescale (SSICPSR), offset 0x010 ......................................................................... 249
Preliminary
July 5, 2006