LM3S310 Luminary Micro, Inc, LM3S310 Datasheet - Page 156

• Manufacturer Part Number: LM3S310
• Description: Lm3s310 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

General-Purpose Timers
156
Reset
Reset
Type
Type
GPTM Control (GPTMCTL)
Offset 0x00C
31:15
11:10
res
RO
RO
31
15
0
0
Bit
14
13
12
9
8
7
TBPWML
Register 4: GPTM Control (GPTMCTL), offset 0x00C
This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer
configuration, and to enable other features such as timer stall and the output trigger.
R/W
RO
30
14
0
0
TBEVENT
TBPWML
TBSTALL
reserved
reserved
reserved
TBOTE
Name
TBEN
TBOTE
R/W
RO
29
13
0
0
res
RO
RO
28
12
0
0
Type
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
R/W
RO
27
11
0
0
TBEVENT
R/W
RO
26
10
0
0
Reset
0
0
0
0
0
0
0
0
TBSTALL
R/W
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
GPTM TimerB PWM Output Level
0: Output is unaffected.
1: Output is inverted.
GPTM TimerB Output Trigger Enable
0: The output TimerB trigger is disabled.
1: The output TimerB trigger is enabled.
Reserved bits return an indeterminate value, and should never
be changed.
GPTM TimerB Event Mode
00: Positive edge.
01: Negative edge.
10: Reserved.
11: Both edges.
GPTM TimerB Stall Enable
0: TimerB stalling is disabled.
1: TimerB stalling is enabled.
GPTM TimerB Enable
0: TimerB is disabled.
1: TimerB is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
Reserved bits return an indeterminate value, and should never
be changed.
TBEN
R/W
RO
24
0
8
0
reserved
res
RO
RO
23
0
7
0
TAPWML
R/W
RO
22
0
6
0
TAOTE
R/W
RO
21
0
5
0
RTCEN
R/W
RO
20
0
4
0
R/W
RO
19
0
3
0
TAEVENT
R/W
RO
18
0
2
0
TASTALL
R/W
RO
17
July 5, 2006
0
1
0
TAEN
R/W
RO
16
0
0
0