LM3S310 Luminary Micro, Inc, LM3S310 Datasheet - Page 299

• Manufacturer Part Number: LM3S310
• Description: Lm3s310 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

July 5, 2006
Reset
Reset
Type
Type
Bit Field
PWMn Interrupt Status (PWMnISC)
RO
RO
31
15
0
0
31:6
5
4
3
2
1
0
Register 19: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C
Register 20: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C
Register 21: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC
These registers provide the current set of interrupt sources that are asserted to the controller
(PWM0ISC controls the PWM generator 0 block, and so on). Bits set to 1 indicate the latched
events that have occurred; a 0 bit indicates that the event in question has not occurred. These are
R/W1C registers; writing a 1 to a bit position clears the corresponding interrupt reason.
RO
RO
30
14
0
0
IntCntLoad
IntCntZero
IntCmpBD
IntCmpBU
IntCmpAD
IntCmpAU
reserved
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
Type
RO
RO
RO
27
11
0
0
reserved
RO
RO
26
10
0
0
Reset
RO
RO
25
0
9
0
0
0
0
0
0
0
0
Preliminary
RO
RO
24
0
8
0
reserved
Description
Reserved bits return an indeterminate value, and should
never be changed.
Indicates that the counter has matched the comparator B
value while counting down.
Indicates that the counter has matched the comparator B
value while counting up.
Indicates that the counter has matched the comparator A
value while counting down.
Indicates that the counter has matched the comparator A
value while counting up.
Indicates that the counter has matched the PWMnLOAD
register.
Indicates that the counter has matched 0.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
IntCmpBD
R/W1C
RO
21
0
5
0
IntCmpBU
R/W1C
RO
20
0
4
0
IntCmpAD
R/W1C
RO
19
0
3
0
IntCmpAU
LM3S310 Data Sheet
R/W1C
RO
18
0
2
0
IntCntLoad
R/W1C
RO
17
0
1
0
IntCntZero
R/W1C
RO
16
0
0
0
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