LM3S310 Luminary Micro, Inc, LM3S310 Datasheet - Page 219

• Manufacturer Part Number: LM3S310
• Description: Lm3s310 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

July 5, 2006
Reset
Reset
Type
Type
UART Interrupt Clear (UARTICR)
Offset 0x044
31:11
RO
RO
31
15
0
0
3:0
Bit
10
9
8
7
6
5
4
Register 12: UART Interrupt Clear (UARTICR), offset 0x044
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
RO
RO
30
14
0
0
reserved
reserved
Name
OEIC
RXIC
BEIC
PEIC
FEIC
RTIC
TXIC
reserved
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
W1C
W1C
W1C
W1C
W1C
W1C
W1C
RO
RO
RO
RO
27
11
0
0
OEIC
W1C
RO
26
10
0
0
Reset
0
0
0
0
0
0
0
0
0
BEIC
W1C
RO
25
0
0
9
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
Overrun Error Interrupt Clear
0: No effect on the interrupt.
1: Clears interrupt.
Break Error Interrupt Clear
0: No effect on the interrupt.
1: Clears interrupt.
Parity Error Interrupt Clear
0: No effect on the interrupt.
1: Clears interrupt.
Framing Error Interrupt Clear
0: No effect on the interrupt.
1: Clears interrupt.
Receive Time-Out Interrupt Clear
0: No effect on the interrupt.
1: Clears interrupt.
Transmit Interrupt Clear
0: No effect on the interrupt.
1: Clears interrupt.
Receive Interrupt Clear
0: No effect on the interrupt.
1: Clears interrupt.
Reserved bits return an indeterminate value, and should never
be changed.
PEIC
W1C
RO
24
0
0
8
reserved
FEIC
W1C
RO
23
0
0
7
RTIC
W1C
RO
22
0
0
6
TXIC
W1C
RO
21
0
0
5
RXIC
W1C
RO
20
0
0
4
RO
RO
0
19
0
3
LM3S310 Data Sheet
RO
RO
0
18
0
2
reserved
RO
RO
0
17
0
1
RO
RO
0
16
0
0
219