LM3S310 Luminary Micro, Inc, LM3S310 Datasheet - Page 84

• Manufacturer Part Number: LM3S310
• Description: Lm3s310 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

System Control
84
Reset
Reset
Type
Type
Bit/Field
31:27
23:19
Run-Mode, Sleep-Mode, and Deep-Sleep-Mode Clock Gating Control 1 (RCGC1, SCGC1, and DCGC1)
Offset 0x104, 0x114, and 0x124
26
25
24
18
RO
RO
31
15
0
0
Register 22: Run-Mode Clock Gating Control 1 (RCGC1), offset 0x104
Register 23: Sleep-Mode Clock Gating Control 1 (SCGC1), offset 0x114
Register 24: Deep-Sleep-Mode Clock Gating Control 1 (DCGC1), offset 0x124
These registers control the clock gating logic. Each bit controls a clock enable for a given
interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled (saving power). The reset state of these bits is 0 (unclocked) unless
otherwise noted, so that all functional units are disabled. It is the responsibility of software to
enable the ports necessary for the application. Note that these registers may contain more bits
than there are interfaces, functions, or units to control. This is to assure reasonable code
compatibility with other family and future parts.
RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and
DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration
(RCC) register (see page 76) specifies that the system uses sleep modes.
RO
RO
30
14
0
0
reserved
reserved
COMP2
COMP1
COMP0
GPTM2
Name
reserved
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
R/W
R/W
R/W
R/W
RO
RO
RO
RO
27
11
0
0
COMP2 COMP1 COMP0
reserved
R/W
RO
26
10
0
0
Reset
R/W
RO
25
0
9
0
0
0
0
0
0
0
Preliminary
R/W
RO
24
0
8
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
This bit controls the clock gating for the Comparator 2
module. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled.
This bit controls the clock gating for the Comparator 1
module. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled.
This bit controls the clock gating for the Comparator 0
module. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled.
Reserved bits return an indeterminate value, and should
never be changed.
This bit controls the clock gating for the General Purpose
Timer 2 module. If set, the unit receives a clock and
functions. Otherwise, the unit is unclocked and disabled.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
reserved
RO
RO
21
0
5
0
SSI
R/W
RO
20
0
4
0
RO
RO
19
0
3
0
reserved
GPTM2 GPTM1 GPTM0
R/W
RO
18
0
2
0
UART1 UART0
R/W
R/W
17
July 5, 2006
0
1
0
R/W
R/W
16
0
0
0