IDT72291L20TFI IDT, Integrated Device Technology Inc, IDT72291L20TFI Datasheet
IDT72291L20TFI
Specifications of IDT72291L20TFI
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IDT72291L20TFI Summary of contents
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FEATURES: • • • • • Choose among the following memory organizations: IDT72281 65,536 x 9 IDT72291 131,072 x 9 • • • • • Pin-compatible with the IDT72261LA/72271LA SuperSync FIFOs • • • • • 10ns read/write cycle time ...
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IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 DESCRIPTION (CONTINUED) The input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data is written into the FIFO on every rising edge ...
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IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 DESCRIPTION (CONTINUED) FWFT mode. HF, PAE and PAF are always available for use, irrespective of timing mode. PAE and PAF can be programmed independently to switch at any point ...
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IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 PIN DESCRIPTION Symbol Name D –D Data Inputs 0 8 MRS Master Reset PRS Partial Reset RT Retransmit FWFT/SI First Word Fall Through/Serial In WCLK Write Clock WEN Write ...
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IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage STG Temperature I DC Output Current OUT NOTE: 1. Stresses greater than those listed ...
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IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 ELECTRICAL CHARACTERISTICS = 5V ± 10%, T (Commercial 0°C to +70°C; Industrial Symbol Parameter f Clock Cycle Frequency S t Data Access Time ...
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IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 FUNCTIONAL DESCRIPTION TIMING MODES: IDT STANDARD VS FIRST WORD FALL THROUGH (FWFT) MODE The IDT72281/72291 support two different timing modes of operation: IDT Standard mode or First Word Fall ...
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IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 TABLE 1 — STATUS FLAGS FOR IDT STANDARD MODE IDT72281 Number of Words 32,768 FIFO 32,769 to (65,536–(m+1)) (65,536–m) 65,536 ...
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IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 IDT72281 (65,536 x 9 ⎯ BIT EMPTY OFFSET (LSB) REGISTER 7FH LOW at Master Reset FFH HIGH at Master Reset 8 ...
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IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 SERIAL PROGRAMMING MODE If Serial Programming mode has been selected, as described above, then programming of PAE and PAF values can be achieved by using a combination of the ...
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IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 RETRANSMIT OPERATION The Retransmit operation allows data that has already been read to be accessed again. There are two stages: first, a setup procedure that resets the read pointer ...
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IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 SIGNAL DESCRIPTION INPUTS: DATA Data inputs for 9-bit wide data. CONTROLS: MASTER RESET (MRS) A Master Reset is accomplished whenever the MRS ...
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IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 WRITE ENABLE (WEN) When the WEN input is LOW, data may be loaded into the FIFO RAM array on the rising edge of every WCLK cycle if the device ...
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IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 valid on the outputs. OR stays LOW after the RCLK LOW to HIGH transition that shifts the last word from the FIFO memory to the outputs. OR goes HIGH ...
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IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 MRS REN WEN t FWFT FWFT/ SEN EF/OR FF/IR PAE PAF RSS t RSS t t RSS ...
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IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 PRS REN WEN RT SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS If FWFT = HIGH, ...
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IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t t ENS ENH REN DATA IN OUTPUT ...
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IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 COMMERCIAL AND INDUSTRIAL 18 TEMPERATURE RANGES ...
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IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 COMMERCIAL AND INDUSTRIAL 19 TEMPERATURE RANGES ...
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IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 RCLK t t ENS ENH t RTS REN WCLK t WEN t ENS RT EF PAE HF PAF NOTES: 1. ...
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IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 RCLK t t ENH ENS t RTS REN WCLK t RTS WEN t ENS RT OR PAE HF PAF NOTES: 1. Retransmit ...
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IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 CLK t CLKH t CLKL WCLK t LDS LD t ENS WEN PAE OFFSET (LSB) Figure 14. Parallel Loading of Programmable ...
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IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 CLKH CLKL WCLK t ENS WEN PAF D - (m+1) words in FIFO RCLK REN NOTES PAF offset maximum FIFO depth. ...
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IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 OPTIONAL CONFIGURATIONS WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting together the control signals of multiple devices. Status flags can be detected from any one device. ...
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IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 • FWFT/SI FWFT/SI WRITE CLOCK WCLK WRITE ENABLE WEN IDT INPUT READY IR 72281 72291 n DATA IN Dn Figure 22. Block Diagram of 131,072 x 9 and 262,144 ...
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ORDERING INFORMATION XXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range product for 15ns and 20ns speed grade are available as a standard device. DATASHEET DOCUMENT HISTORY 04/24/2001 pgs and 26. 01/13/2009 pg. 26. ...