IDT72291L20TFI IDT, Integrated Device Technology Inc, IDT72291L20TFI Datasheet - Page 23

• Manufacturer Part Number: IDT72291L20TFI
• Description: IC FIFO 65536X18 LP 20NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72291L20TFI

• Function: Synchronous
• Memory Size: 1.1M (65K x 18)
• Data Rate: 50MHz
• Access Time: 20ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-STQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72291L20TFI

NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
3. t
4. PAF is asserted and updated on the rising edge of WCLK only.
NOTES:
1. n = PAE offset.
2. For IDT Standard mode.
3. For FWFT mode.
4. t
5. PAE is asserted and updated on the rising edge of WCLK only.
NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 65,536 for the IDT72281 and 131,072 for the IDT72291.
2. For FWFT mode: D = maximum FIFO depth. D = 65,537 for the IDT72281 and 131,073 for the IDT72291.
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
In IDT Standard mode: D = 65,536 for the IDT72281 and 131,072 for the IDT72291.
In FWFT mode: D = 65,537 for the IDT72281 and 131,073 for the IDT72291.
the rising edge of RCLK and the rising edge of WCLK is less than t
the rising edge of WCLK and the rising edge of RCLK is less than t
SKEW2
SKEW2
WCLK
RCLK
WEN
REN
WCLK
RCLK
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
PAE
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus t
WEN
REN
PAF
t
CLKH
WCLK
RCLK
WEN
REN
t
HF
CLKH
t
ENS
Figure 19. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
n words in FIFO
n+1 words in FIFO
Figure 18. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
t
ENS
t
CLKL
D - (m+1) words in FIFO
t
t
Figure 20. Half-Full Flag Timing (IDT Standard and FWFT Modes)
ENH
t
SKEW2
CLKL
1
(2)
,
(3)
t
ENH
(4)
[
D-1
2
D/2 words in FIFO
+ 1
]
t
PAE
words in FIFO
1
t
CLKH
(2)
2
(1)
,
SKEW2
SKEW2
(2)
t
ENS
, then the PAF deassertion time may be delayed one extra WCLK cycle.
, then the PAE deassertion may be delayed one extra RCLK cycle.
t
CLKL
2
t
23
PAF
t
t
ENH
ENS
t
HF
t
ENS
t
SKEW2
t
n+1 words in FIFO
n+2 words in FIFO
ENS
(3)
[
D-1
D/2 + 1 words in FIFO
2
t
+ 2
ENH
]
words in FIFO
D - m words in FIFO
t
ENH
(2)
(3)
t
,
HF
1
(1)
1
,
(2)
(2)
COMMERCIAL AND INDUSTRIAL
[
D-1
2
D/2 words in FIFO
t
+ 1
PAE
2
]
words in FIFO
TEMPERATURE RANGES
t
2
PAF
4675 drw 23
n words in FIFO
n+1 words in FIFO
PAE
(1)
PAF
,
(2)
). If the time between
D-(m+1) words
in FIFO
). If the time between
4675 drw 21
4675 drw 22
(2)
(2)
,
(3)