IDT72291L20TFI IDT, Integrated Device Technology Inc, IDT72291L20TFI Datasheet - Page 24

• Manufacturer Part Number: IDT72291L20TFI
• Description: IC FIFO 65536X18 LP 20NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72291L20TFI

• Function: Synchronous
• Memory Size: 1.1M (65K x 18)
• Data Rate: 50MHz
• Access Time: 20ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-STQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72291L20TFI

OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
signals of multiple devices. Status flags can be detected from any one device.
The exceptions are the EF and FF functions in IDT Standard mode and the IR
and OR functions in FWFT mode. Because of variations in skew between RCLK
and WCLK, it is possible for EF/FF deassertion and IR/OR assertion to vary
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
Word width may be increased simply by connecting together the control
GATE
(1)
FIRST WORD FALL THROUGH/
DATA IN
SERIAL INPUT (FWFT/SI)
MASTER RESET (MRS)
PARTIAL RESET (PRS)
FULL FLAG/INPUT READY (FF/IR)
FULL FLAG/INPUT READY (FF/IR) #2
RETRANSMIT (RT)
m + n
PROGRAMMABLE (PAF)
Figure 21. Block Diagram of 65,536 x 18 and 131,072 x 18 Width Expansion
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
HALF-FULL FLAG (HF)
D
0
- Dm
LOAD (LD)
m
#1
72281
72291
IDT
FIFO
#1
Dm
m
+1
- Dn
Q
24
0
n
- Qm
by one cycle between FIFOs. In IDT Standard mode, such problems can be
avoided by creating composite flags, that is, ANDing EF of every FIFO, and
separately ANDing FF of every FIFO. In FWFT mode, composite flags can be
created by ORing OR of every FIFO, and separately ORing IR of every FIFO.
devices. D
each device form a 18-bit wide output bus. Any word width can be attained by
adding additional IDT72281/72291 devices.
Figure 23 demonstrates a width expansion using two IDT72281/72291
72281
72291
FIFO
IDT
#2
0
- D
8
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
EMPTY FLAG/OUTPUT READY (EF/OR) #2
n
EMPTY FLAG/OUTPUT READY (EF/OR) #1
from each device form a 18-bit wide input bus and Q
PROGRAMMABLE (PAE)
Qm
+1
- Qn
m + n
COMMERCIAL AND INDUSTRIAL
DATA OUT
TEMPERATURE RANGES
4675 drw 24
GATE
(1)
0
-Q
8
from