IDT72291L20TFI IDT, Integrated Device Technology Inc, IDT72291L20TFI Datasheet - Page 3

• Manufacturer Part Number: IDT72291L20TFI
• Description: IC FIFO 65536X18 LP 20NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72291L20TFI

• Function: Synchronous
• Memory Size: 1.1M (65K x 18)
• Data Rate: 50MHz
• Access Time: 20ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-STQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72291L20TFI

DESCRIPTION (CONTINUED)
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
FWFT mode. HF, PAE and PAF are always available for use, irrespective of
timing mode.
memory. (See Table I and Table II.) Programmable offsets determine the flag
switching threshold and can be loaded by two methods: parallel or serial. Two
default offset settings are also provided, so that PAE can be set to switch at 127
or 1,023 locations from the empty boundary and the PAF threshold can be set
at 127 or 1,023 locations from the full boundary. These choices are made with
the LD pin during Master Reset.
are used to load the offset registers via the Serial Input (SI). For parallel
programming, WEN together with LD on each rising edge of WCLK, are used
to load the offset registers via D
of RCLK can be used to read the offsets in parallel from Qn regardless of whether
serial or parallel offset loading has been selected.
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
PAE and PAF can be programmed independently to switch at any point in
For serial programming, SEN together with LD on each rising edge of WCLK,
During Master Reset (MRS) the following events occur: The read and write
FIRST WORD FALL THROUGH/SERIAL INPUT
PROGRAMMABLE ALMOST-FULL (PAF)
FULL FLAG/INPUT READY (FF/IR)
n
Figure 1. Block Diagram of Single 65,536 x 9 and 131,072 x 9 Synchronous FIFO
. REN together with LD on each rising edge
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
SERIAL ENABLE(SEN)
DATA IN (D
PARTIAL RESET (PRS)
LOAD (LD)
(FWFT/SI)
0
- D
n
)
72281
72291
3
IDT
Standard mode or FWFT mode. The LD pin selects either a partial flag default
setting of 127 with parallel programming or a partial flag default setting of 1,023
with serial programming. The flags are updated according to the timing mode
and default offsets selected.
location of the memory. However, the timing mode, partial flag programming
method, and default or programmed offset settings existing before Partial Reset
remain unchanged. The flags are updated according to the timing mode and
offsets in effect. PRS is useful for resetting a device in mid-operation, when
reprogramming partial flags would be undesirable.
once. A LOW on the RT input during a rising RCLK edge initiates a retransmit
operation by setting the read pointer to the first location of the memory array.
automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
CMOS technology.
MASTER RESET (MRS)
The Partial Reset (PRS) also sets the read and write pointers to the first
The Retransmit function allows data to be reread from the FIFO more than
If, at any time, the FIFO is not actively performing an operation, the chip will
The IDT72281/72291 are fabricated using IDT’s high speed submicron
READ CLOCK (RCLK)
READ ENABLE (REN)
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF-FULL FLAG (HF)
DATA OUT (Q
OUTPUT ENABLE (OE)
0
- Q
n
COMMERCIAL AND INDUSTRIAL
)
TEMPERATURE RANGES
4675 drw 03