IDT72291L20TFI IDT, Integrated Device Technology Inc, IDT72291L20TFI Datasheet - Page 9

• Manufacturer Part Number: IDT72291L20TFI
• Description: IC FIFO 65536X18 LP 20NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72291L20TFI

• Function: Synchronous
• Memory Size: 1.1M (65K x 18)
• Data Rate: 50MHz
• Access Time: 20ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-STQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72291L20TFI

NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
LD
0
0
0
X
1
1
1
WEN
8
8
8
8
X
0
1
1
1
0
1
7
7
7
7
REN
X
1
0
1
1
0
1
IDT72281 (65,536 x 9 ⎯ BIT)
EMPTY OFFSET (LSB) REGISTER
FULL OFFSET (MSB) REGISTER
03H if LD is HIGH at Master Reset
00H if LD is LOW at Master Reset
SEN
FFH if LD is HIGH at Master Reset
7FH if LD is LOW at Master Reset
EMPTY OFFSET (MSB) REGISTER
1
1
X
X
X
1
0
FULL OFFSET (LSB) REGISTER
FFH if LD is HIGH at Master Reset
7FH if LD is LOW at Master Reset
00H if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
DEFAULT VALUE
DEFAULT VALUE
Figure 4. Programmable Flag Offset Programming Sequence
DEFAULT VALUE
DEFAULT VALUE
WCLK
Figure 3. Offset Register Location and Default Values
X
X
X
X
RCLK
X
X
X
X
X
Parallel write to registers:
Empty Offset (MSB)
Serial shift into registers:
32 bits for the IDT72281
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Empty Offset (LSB)
Full Offset (LSB)
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Write Memory
Read Memory
No Operation
Ending with Full Offset (MSB)
No Operation
0
0
0
0
9
IDT72281
8
8
8
8
8
8
7
7
7
7
IDT72291 (131,072 x 9 ⎯ BIT)
FULL OFFSET (MID-BYTE) REGISTER
03H if LD is HIGH at Master Reset
00H if LD is LOW at Master Reset
EMPTY OFFSET (MID-BYTE) REGISTER
EMPTY OFFSET (LSB) REGISTER
FFH if LD is HIGH at Master Reset
7FH if LD is LOW at Master Reset
FULL OFFSET (LSB) REGISTER
FFH if LD is HIGH at Master Reset
7FH if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
00H if LD is LOW at Master Reset
DEFAULT VALUE
DEFAULT VALUE
Parallel write to registers:
Empty Offset (LSB)
Full Offset (LSB)
Full Offset (Mid-Byte)
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (Mid-Byte)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (Mid-Byte)
Full Offset (MSB)
Serial shift into registers:
34 bits for the IDT72291
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Write Memory
Read Memory
No Operation
Empty Offset (Mid-Byte)
Empty Offset (MSB)
No Operation
DEFAULT VALUE
DEFAULT VALUE
COMMERCIAL AND INDUSTRIAL
IDT72291
1
1
(MSB) REGISTER
(MSB) REGISTER
EMPTY OFFSET
DEFAULT
FULL OFFSET
DEFAULT
4675 drw06
0H
0H
TEMPERATURE RANGES
0
0
0
0
0
0
4675 drw07