IDT72291L20TFI IDT, Integrated Device Technology Inc, IDT72291L20TFI Datasheet - Page 2

• Manufacturer Part Number: IDT72291L20TFI
• Description: IC FIFO 65536X18 LP 20NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72291L20TFI

• Function: Synchronous
• Memory Size: 1.1M (65K x 18)
• Data Rate: 50MHz
• Access Time: 20ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-STQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72291L20TFI

(WEN) input. Data is written into the FIFO on every rising edge of WCLK when
WEN is asserted. The output port is controlled by a Read Clock (RCLK) input
and Read Enable (REN) input. Data is read from the FIFO on every rising edge
of RCLK when REN is asserted. An Output Enable (OE) input is provided for
three-state control of the outputs.
to f
of the one clock input with respect to the other.
Standard mode and First Word Fall Through (FWFT) mode.
on the data output lines unless a specific read operation is performed. A read
PIN CONFIGURATIONS
NOTES:
1. DC = Don’t Care. Must be tied to GND or V
2. This pin may either be tied to GND or left open.
3. DNC = Do Not Connect.
DESCRIPTION (CONTINUED)
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
The input port is controlled by a Write Clock (WCLK) input and a Write Enable
The frequencies of both the RCLK and the WCLK signals may vary from 0
In IDT Standard mode, the first word written to an empty FIFO will not appear
MAX
There are two possible timing modes of operation with these devices: IDT
with complete independence. There are no restrictions on the frequency
PIN 1
GND
GND
GND
GND
GND
GND
GND
GND
GND
WEN
DC
SEN
V
V
D8
D7
CC
CC
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
CC
, cannot be left open.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TQFP (PN64-1, ORDER CODE: PF)
STQFP (PP64-1, ORDER CODE: TF)
TOP VIEW
2
operation, which consists of activating REN and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
the data output lines after three transitions of the RCLK signal. A REN does not
have to be asserted for accessing the first word. However, subsequent words
written to the FIFO do require a LOW on REN for access. The state of the FWFT/
SI input during Master Reset determines the timing mode in use.
provide, the FWFT timing mode permits depth expansion by chaining FIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.
IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable Almost-
Empty flag) and PAF (Programmable Almost-Full flag). The EF and FF functions
are selected in IDT Standard mode. The IR and OR functions are selected in
In FWFT mode, the first word written to an empty FIFO is clocked directly to
For applications requiring more data storage capacity than a single FIFO can
These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready), FF/
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
COMMERCIAL AND INDUSTRIAL
4675 drw 02
DNC
DNC
GND
DNC
DNC
V
DNC
DNC
DNC
GND
DNC
DNC
Q8
Q7
Q6
GND
TEMPERATURE RANGES
CC
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)