MT90868 Zarlink Semiconductor, Inc., MT90868 Datasheet - Page 15

• Manufacturer Part Number: MT90868
• Description: High Bandwidth Digital Switch - 8,192 x 8,192 channels among local streams and 1,024 x 1,024 channels among two selected backplane streams
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
Switching Configuration
The MT90868 has two operation modes at different
data rates for the backplane interface and one
operation mode for the local interface. The two
operation modes for the backplane interface can be
selected via the backplane mode selection bit (BMS)
in the Control Register (CR).
Backplane Interface
The backplane interface can be programmed to
accept data streams of 16Mb/s or 32Mb/s. When
BMS bit of the CR register is low, the 16Mb/s mode
is enabled, BSTi0-63 and BSTo0-63 have a data rate
of 16.384Mb/s. When BMS = 1, the 32Mb/s mode is
enabled, BSTi0-63 and BSTo0-63 have a data rate
of 32.768Mb/s. Table 1 describes the data rates and
mode selections for the backplane interface.
Local Interface
The local interface has one mode of operation which
can only operate at the data rate of 8.192Mb/s.
Output Bit Advancement Selection
The device allows users to advance individual
backplane or local output streams with respect to the
Bit Advancement = -1/8
Bit Advancement = -1/4
Bit Advancement = -3/8
BMS bit of the Control Register
Bit Advancement = 0
Figure 7 - Local Output Advancement Timing Diagram when the Data Rate is 8Mb/s
(Default)
LSToX
LSToX
LSToX
LSToX
FP8o
C8o
0
1
Bit 1
Table 1 - Mode Selection for Backplane Streams
Bit 1
Bit 1
Ch127
Bit 1
Ch127
Bit Advancement, -3/8
Ch127
Bit Advancement, -1/4
Ch127
Bit Advancement, -1/8
16.384Mb/s
32.768Mb/s
Bit 0
Modes
Bit 0
Bit 0
Bit 0
frame
compensating variable output delays caused by
various output loading conditions. Each output
stream can have its own advancement value
programmed by the output advancement registers.
The
(BOAR0 to BOAR7) are used to program the
backplane output advancement. The local output
advancement registers (LOAR0 to LOAR7) are used
to program the local output advancement. See Tables
17 and Table 19 for the descriptions of the LOAR and
BOAR registers.
Possible adjustment for local is -1/8, -1/4 or -3/8 bit
and the resolution is 1/8 bit (or 1/8 of C8o cycle). For
backplane, the possible adjustment is -1/4, -1/2 or -3/4
bit when the output data rate is 16.384Mb/s. When the
backplane data rate is 32.768Mb/s, the possible
adjustment is -1/2, -1 or -1 1/2 bit. For both data rates,
the resolution is 1/8 of C8i cycle. The advancement is
independent of the output data rate. Figures 7, 8
and 9 describe the details of the output advancement
programming for the local and the backplane
interfaces respectively.
Input Bit Delay Selection
The MT90868 input bit delay features allow users to
have more flexibility when designing the switch
matrices at high speed, in which the delay lines are
easily created on PCM highways which are
Bit 7
Bit 7
backplane
boundary.
Bit 7
Bit 7
Ch0
BSTi0 - 63 and BSTo0 - 63
BSTi0 - 63 and BSTo0 - 63
Ch0
Backplane Interface
Ch0
output
Ch0
This
Bit 6
Bit 6
Bit 6
advancement
feature
Bit 6
MT90868
is
useful
registers
15
in