MT90868 Zarlink Semiconductor, Inc., MT90868 Datasheet - Page 27

• Manufacturer Part Number: MT90868
• Description: High Bandwidth Digital Switch - 8,192 x 8,192 channels among local streams and 1,024 x 1,024 channels among two selected backplane streams
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
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JTAG Support
The MT90868 JTAG interface conforms to the
Boundary-Scan IEEE1149.1 standard. The operation
of the boundary-scan circuitry is controlled by an
external Test Access Port (TAP) Controller. See
Figure 24 for the JTAG test port timing.
Test Access Port (TAP)
The Test Access Port (TAP) accesses the MT90868
test functions. It consists of four input pins and one
output pin as follows:
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tristate on LSTo0-63, LCSTo0-3 and BSTo)-63
outputs.
Set bit 11, STBY, of the Control Register (CR)
to high for normal functional mode.
Test Clock Input (TCK)
TCK provides the clock for the test logic. The
TCK does not interfere with any on-chip clock
and thus remains independent in the functional
mode. The TCK permits shifting of test data into
or out of the Boundary-Scan register cells
concurrently with the operation of the device
and without interfering with the on-chip logic.
Test Mode Select Input (TMS)
The TAP Controller uses the logic signals
received at the TMS input to control test
operations. The TMS signals are sampled at
the rising edge of the TCK pulse. This pin is
internally pulled to Vdd when it is not driven
from an external source.
Test Data Input (TDi)
Serial input data applied to this port is fed either
into the instruction register or into a test data
register, depending on the sequence previously
applied to the TMS input. Both registers are
described in a subsequent section. The
received input data is sampled at the rising
edge of TCK pulses. This pin is internally pulled
to Vdd when it is not driven from an external
source.
Test Data Output (TDo)
Depending on the sequence previously applied
to the TMS input, the contents of either the
instruction register or data register are serially
shifted out towards the TDO. The data out of
the TDO is clocked on the falling edge of the
TCK pulses. When no data is shifted through
the boundary scan cells, the TDO driver is set
to a high impedance state.
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Instruction Register
The MT90868 uses the public instructions defined in
the IEEE 1149.1 standard. The JTAG Interface
contains a four-bit instruction register. Instructions
are serially loaded into the instruction register from
the TDI when the TAP Controller is in its shifted-IR
state. These instructions are subsequently decoded
to achieve two basic functions: to select the test data
register that may operate while the instruction is
current and to define the serial test data register path
that is used to shift data between TDI and TDO
during data register scanning.
Test Data Register
As specified in IEEE 1149.1, the MT90868 JTAG
Interface contains three test data registers:
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Version<31:28>: 0000
Part No. <27:12>: 0000 1000 0110 1000
Manufacturer ID<11:1>: 0001 0100 101
LSB<0>: 1
BSDL
A BSDL (Boundary Scan Description Language) file
is available from Zarlink Semiconductor to support
the use of the IEEE 1149 test interface.
Test Reset (TRST)
It resets the JTAG scan structure. This pin is
internally pulled to Vdd when it is not driven
from an external source.
The Boundary-Scan Register
The Boundary-Scan register consists of a
series of Boundary-Scan cells arranged to form
a scan path around the boundary of the
MT90868 core logic.
The Bypass Register
The Bypass register is a single stage shift
register that provides a one-bit path from TDi to
its TDo.
The Device Identification Register
The JTAG device ID for the MT90868 is
0086814BH.
MT90868
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