MT90868 Zarlink Semiconductor, Inc., MT90868 Datasheet - Page 19

• Manufacturer Part Number: MT90868
• Description: High Bandwidth Digital Switch - 8,192 x 8,192 channels among local streams and 1,024 x 1,024 channels among two selected backplane streams
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
Memory Block Programming
The block programming register (BPR) provides
users with the capability of initializing the local and
backplane connection memories in two frames. The
local connection memory is partitioned into local
connection memory high (LCMH) and the local
connection memory low (LCML). Bit 13 - bit 15 of
every backplane connection memory location will be
programmed with the pattern stored in bit 4 - bit 6 of
the BPR register. Bit 15 of every LCML location and
bit 0 - bit 1 of every LCMH location will be
programmed with the pattern stored in bits 1 to 3 of
the BPR register. The other bit positions of the
backplane connection memory, the local connection
memory low and all bits of the local connection
memory high are loaded with zeros. See Figure 15 for
the connection memory contents when the device is
in the block programming mode.
The block programming mode is enabled by setting
the memory block program (MBP) bit of the control
register to high. When the block programming enable
(BPE) bit of the BPR register is set to high, the block
programming data will be loaded into bits 13 to 15 of
every backplane connection memory location and
bits 15 of every local connection memory low and
bit 0 to bit 1 of every local connection memory high
location. The other connection memory bits are
loaded with zeros. It takes two frames (250 s) to
allow the backplane and local connection memories
to be loaded. Upon the completion of the memory
block programming, the device resets the BPE bit to
low to indicating that the process is finished. See
Table 6 for the bit assignment of the BPR register.
BBPD2
LBPD0
15
15
15
0
BBPD
14
14
14
0
0
1
BBPD0
13
13
13
0
0
Figure 15 - Block Programming Data in the Connection Memories
0
12
12
12
0
0
11
11
11
0
0
0
Local Connection Memory Low (LCMH)
Backplane Connection Memory (BCM)
Local Connection Memory Low (LCML)
10
10
10
0
0
0
9
9
9
0
0
0
8
8
8
0
0
0
Switching Paths
The MT90868 provides users with four switching
paths,
backplane", "backplane-to-backplane" and "local-to-
local". The switching configuration is controlled by
programming the local connection and the backplane
connection memories.
The "backplane-to-local" switching path allows the
device to perform data switching between the
backplane input port and the local output port among
32,768 backplane input channels and 8,192 local
output channels. The local connection memory
determines the switching configurations. See Table
30 and Table 31 for the details.
The "local-to-backplane" switching path allows users
to perform data switching between the local input
port and the backplane output port among 8,192
local input channels and 16,380 or 32,760 backplane
output channels when operated in the 16Mb/s or
32Mb/s mode respectively. The last channel (Ch255
or Ch511) of the backplane output streams BSTo60
to BSTo63 or BSTo58 to BSTo63 contains invalid
output data for the 16Mb/s or 32Mb/s mode
respectively. Avoid using the last channel of these
streams for the "local-to-backplane" data switching.
The backplane connection memory determines the
switching configurations. See Table 32 for the
details.
The "local-to-local" switching path allows users to
perform data switching between the local input and
the local output ports among 8,192 local input and
8,192 local output ports. The local connection
7
7
7
0
0
0
6
6
6
0
0
0
namely
5
5
5
0
0
0
4
4
4
0
0
0
"backplane-to-local",
3
3
3
0
0
0
2
2
2
0
0
0
LBPD2
MT90868
1
1
1
0
0
LBPD1
"local-to-
0
0
0
0
0
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