MT90868 Zarlink Semiconductor, Inc., MT90868 Datasheet - Page 20

• Manufacturer Part Number: MT90868
• Description: High Bandwidth Digital Switch - 8,192 x 8,192 channels among local streams and 1,024 x 1,024 channels among two selected backplane streams
• Manufacturer: Zarlink Semiconductor, Inc.

MT90868
20
Microprocessor Interface
The MT90868 provides a microprocessor port
interface for non-multiplexed bus structures. This
interface is compatible to Motorola non-multiplexed
bus
microprocessor signals are the 16-bit parallel data
bus (D15 - D0), 16-bit address bus (A15 - A0) and
four control lines (CS, DS, R/W and DTA). See
Figure 23 for details on the Motorola non-multiplexed
bus timing.
The MT90868 synchronous microprocessor port
provides access to the internal registers, the
connection and the data memories. All memory
memory determines the switching configurations.
See Table 30 and Table 31 for the details.
The "backplane-to-backplane" switching path allows
users to perform data switching between the
backplane input and the backplane output ports. In
this switching mode, only two backplane input
streams can be selected by the backplane data input
selection register (BDISR). The switching capacity is
512 x 512 or 1,024 x 1,024 backplane channels for
the 16Mb/s or 32Mb/s mode respectively. The
BDISR register selects two backplane input data
streams, namely, Stream A and Stream B to support
the
backplane
switching configurations. See Table 33 for the
details.
Throughput Delay
The usage of the local input channel delay buffer and
the local output channel advancement buffer affects
Local-to-Backplane
Local-to-Local
Backplane-to-Local
Backplane-to-backplane
** Note: Input Buffer = Local input channel delay buffer
Switching Path
"backplane-to-backplane"
structure
Output Buffer = Local output channel advancement buffer.
connection
Table 2 - Data Delay Through the Device via Different Switching Paths
specification.
memory
Output Buffer** OFF
Input Buffer** OFF
1 Frame + 2 Ch
(LOCAEN = 0)
(LICDEN = 0)
2 Frames
2 Frames
2 Frames
switching.
determines
The
required
The
the
Output Buffer OFF
1 Frame + 2 Ch
Input Buffer ON
(LOCAEN = 0)
(LICDEN = 1)
3 Frames
3 Frames
2 Frames
mapping locations are read/write accessible except
the local and backplane bit error rate count registers
(LBCR and BBCR) and data memories which can
only be read by the users.
Address Mapping of Registers and Memories
The address bus of the microprocessor port interface
selects the internal registers and the memories. If
the address bit, A15 is low, then the registers are
addressed by A14 to A0 as shown in Table 3.
If A15 is high, the remaining address input lines are
used to select the data and connection memory
positions corresponding to the serial input or output
data streams as shown in Table 4.
the data throughput delay for the four data switching
paths. The usage of these two buffers is controlled
by the LICDEN and the LOCAEN bits in the control
register (CR). When LICDEN and LOCAEN bits are
low, the "backplane-to-local" switching path has a
throughput delay of one frame plus 2 channel slots;
the
backplane" and the "local-to-local" switching paths
have the throughput delay of two frames.
When the local input data streams pass through the
local input channel delay buffer to perform the input
channel adjustment by setting the LICDEN bit to
high, the device will add one more frame data to the
"local-to-backplane" and the "local-to-local" data
switching paths. When the local output data streams
pass through the local output channel advancement
buffer to perform the output channel adjustment by
setting the LOCAEN bit to high, the device will add
one more frame data delay to the "backplane-to-
local" and the "local-to-local" switching paths.
Table 2 describes the different delay throughput for
the various data switching paths.
Data Delay
"local-to-backplane",
2 Frames + 2 Ch
Output Buffer ON
Input Buffer OFF
(LOCAEN = 1)
(LICDEN = 0)
3 Frames
2 Frames
2 Frames
Advance Information
the
2 Frames + 2 Ch
Output Buffer ON
Input Buffer ON
(LOCAEN = 1)
(LICDEN = 1)
3 Frames
4 Frames
2 Frames
"backplane-to-