MT90868 Zarlink Semiconductor, Inc., MT90868 Datasheet - Page 28

• Manufacturer Part Number: MT90868
• Description: High Bandwidth Digital Switch - 8,192 x 8,192 channels among local streams and 1,024 x 1,024 channels among two selected backplane streams
• Manufacturer: Zarlink Semiconductor, Inc.

MT90868
Registers Description
28
BHIZ
15
Bit
Read/Write Address: 0000
Reset Value: 0000
15
14
13
12
11
10
9
8
7
6
5
4
LOCAEN
LOCAEN
14
LICDEN
Unused
CBERB
SBERB
CBERL
SBERL
Name
STBY
PRST
BHIZ
BMS
MBP
LICDEN
H
13
Backplane Tristate or Driven-High Control: When this bit is low, the backplane outputs
support the per-channel tristate feature. When this bit is high, the backplane outputs
support the per-channel driven high feature.
Local Output Channel Advancement Enable: When this bit is high, the Local Output
Channel Advancement is enabled and the local output data will pass through the local
output channel advancement buffer as shown in Figure 1. The local output channel
advancement registers (LOCAR31 - LOCAR0) control the channel advancement from 0 to
127 channels. When this bit is low, the channel advancement is disabled (default
condition) and the local output data will bypass the local output channel advancement
buffer.
Local Input Channel Delay Enable: When this bit is high, the Local Input Channel
Advancement is enabled and the local input data will pass through the local input channel
delay buffer as shown in Figure 1. The local input channel delay registers (LICDR31 -
LICDR0) control the channel delay from 0 to 127 channels. When this bit is low, the
channel delay is disabled (default condition) and the local input data will bypass the local
input channel delay buffer.
Reserved. In normal functional mode, this bit MUST be set to zero.
StandBy: In normal functional mode, this bit MUST be set to one after power up.
PRBS Reset: When this bit is high, the output of the BER transmitter will be initialized.
Backplane Bit Error Rate Clear: When this bit is high, it resets the backplane internal bit
error counter and the content of the backplane bit error count register (BBCR) to zero.
Upon completion of the reset, set this bit to zero.
Backplane Bit Error Rate Test Start: When this bit is high, it enables the backplane BER
transmitter and receiver; starts the backplane bit error rate test. The bit error test result is
kept in the backplane bit error count (BBCR) register. Upon the completion of the BER
test, set this bit to zero.
Local Bit Error Rate Clear: When this bit is high, it resets the local internal bit error
counter and the content of the local bit error count register (LBCR) to zero. Upon
completion of the reset, set this bit to zero.
Local Start Bit Error Rate Test: When this bit is high, it enables the local BER
transmitter and receiver; starts the local bit error rate test. The bit error test result is kept in
the local bit error count (LBCR) register. Upon the completion of the BER test, set this bit
to zero.
Backplane Mode Select: When the BIME pin is low and this bit is low, it enables the
16Mb/s mode and BSTi0-63 and BSTo0-63 have data rate of 16.384Mb/s. When the
BIME pin is low and this bit is high, it enables the 32Mb/s mode and BSTi0-63 and BSTo0-
63 have data rate of 32.768Mb/s. When the BIME pin is high, set this bit to high to enable
the bit interleaving mode operation.
Memory Block Programming: When this bit is high, the connection memory block
programming mode is enabled to program Bit 15 of the Local Connection Memory Low,
Bit 0 and Bit 1 of the Local Connection Memory High and Bit 13 to Bit 15 of the Backplane
Connection Memory. When it is low, the memory block programming mode is disabled.
Refer to Figure 15 for details.
H
12
0
STBY
11
Table 5 - Control Register (CR) Bits
PRST
10
CBERB
9
SBERB
8
Description
CBERL
7
SBERL
6
BMS
5
Advance Information
MBP
4
OSB
3
MS2
2
MS1
1
MS0
0