IDT72T54252L6-7BB IDT, Integrated Device Technology Inc, IDT72T54252L6-7BB Datasheet - Page 19

• Manufacturer Part Number: IDT72T54252L6-7BB
• Description: IC FIFO DDR/SDR QUAD/DUAL 324BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T54252L6-7BB

• Function: Asynchronous
• Memory Size: 20K (1K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T54252L6-7BB

TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
of operation: IDT Standard mode and First Word Fall Through (FWFT) mode.
The selection of which mode will be used is determined during master reset, by
the state of the FWFT input.
be selected. This mode uses the Empty Flag (EF) to indicate whether or not there
are any words present in the FIFO. It also uses the Full Flag (FF) to indicate
whether or not the FIFO has any free space for writing. In IDT Standard mode,
every word read from the FIFO, including the first, must be requested using the
Read Enable (REN), Read Chip Select (RCS), and RCLK.
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs. It also uses Input Ready (IR) to indicate whether
or not the FIFO has any free space for writing. In the FWFT mode, the first word
written to an empty FIFO goes directly to output bus after three RCLK rising
edges. Applying REN = LOW is not necessary, although having RCS = 0 at the
previous rising RCLK is necessary to keep the output from being in high-
impedance. However, subsequent words must be accessed using Read
Enable (REN), Read Chip Select (RCS), and RCLK. Various signals in both
inputs and outputs operate differently depending on which timing mode is in effect.
The timing mode selected affects all internal FIFOs and are not programmed
individually.
IDT STANDARD MODE
outlined in Table 3, Status Flags for IDT Standard Mode. To write data into the
FIFO, Write Enable (WEN), and Write Chip Select (WCS) must be LOW. Data
presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of the Write Clock (WCLK). After the first write is performed, the Empty
Flag (EF) will go HIGH. Subsequent writes will continue to fill up the FIFO. The
Programmable Almost-Empty flag (PAE) will go HIGH after n + 1 words have
been loaded into the FIFO, where "n" is the empty offset value. The default
NOTES:
1. These registers are not used in Dual mode. They are not programmed or read in the serial chain.
2. In all modes, the higher numbered bit is the MSB. For example, in the IDT72T54242 in Quad mode, the first bit is the LSB for PAE3.
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
The IDT72T54242/72T54252/72T54262 support two different timing modes
During master reset, if the FWFT pin is LOW, then IDT Standard mode will
If the FWFT pin is HIGH during master reset, then FWFT mode will be
In this mode, the status flags FF, PAF, PAE, and EF operate in the manner
Serial Bits
IDT72T54242
Quad mode
1 - 15
16 - 30
31 - 45
46 - 60
61 - 75
76 - 90
91 - 105
106 - 120
IDT72T54252
Quad mode
1 - 16
17 - 32
33 - 48
49 - 64
65 - 80
81 - 96
97 - 112
113 - 128
Figure 4. Offset Registers Serial Bit Sequence
IDT72T54262
Quad mode
1 - 17
18 - 34
35 - 51
52 - 68
69 - 85
86 - 102
103 - 119
120 - 136
IDT72T54242
Dual mode
IW/OW = x20
1 - 14
15 - 28
29 - 42
43 - 56
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⎯
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™
19
DDR/SDR FIFO
settings for these values are listed in Table 2. This parameter is also user
programmable as described in the Serial Writing and Reading of Offset Registers
section.
cause the Programmable Almost-Full flag (PAF) to go LOW. Again, if no reads
are performed, the PAF will go LOW after (32,768-m) writes for the IDT72T54242,
(65,536-m) writes for the IDT72T54252, and (131,072-m) writes for the
IDT72T54262. In x20 dual mode, PAF will go LOW after (16,384-m) writes for
the IDT72T54242, (32,768-m) writes for the IDT72T54252, and (65,536-m)
writes for the IDT72T54262. The offset “m” is the full offset value. The default
setting for these values are listed in Table 3, Status Flags for IDT Standard
Mode. This parameter is also user programmable. See the section on Serial
Writing and Reading of Offset Registers for details.
operations. If no reads are performed after a reset, FF will go LOW after D writes
to the FIFO, where D = 32,768 writes for the IDT72T54242, 65,536 writes for
the IDT72T54252, and 131,072 writes for the IDT72T54262. In x20 dual mode,
FF will go LOW after 16,384 writes for the IDT72T54242, 32,768 writes for the
IDT72T54252, and 65,536 writes for the IDT72T54262.
read operations will cause PAF to go HIGH at the conditions described in Table
3, Status Flags for IDT Standard Mode. If further read operations occur without
write operations, PAE will go LOW when there are n words in the FIFO, where
n is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO, the EF will
go LOW inhibiting further read operations. REN is ignored when the FIFO is
empty, but RCS will continue to determine whether or not the output is in high-
impedance.
register-buffered outputs. IDT Standard mode is available when the device is
configured in either Single Data Rate or Double Data Rate mode. Relevant
timing diagrams for IDT Standard mode can be found in Figure 10, 11, 12, 13,
14, 15, 16, 17, 18 and 23.
Continuing to write data into the FIFO without performing read operations will
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write
If the FIFO is full, the first read operation will cause FF to go HIGH. Subsequent
When configured in IDT Standard mode, the EF and FF outputs are double
IDT72T54242
Dual mode
IW/OW = x10
or
IDT72T54252
IW/OW = x20
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⎯
1 - 15
16 - 30
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⎯
31 - 45
46 - 60
IDT72T54252
Dual mode
IW/OW = x10
or
IDT72T54262
IW/OW = x20
1 - 16
17 - 32
33 - 48
49 - 64
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⎯
⎯
⎯
COMMERCIAL AND INDUSTRIAL
IDT72T54262
Dual mode
IW/OW = x10
TEMPERATURE RANGES
1 - 17
18 - 34
35 - 51
52 - 68
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FEBRUARY 11, 2009
Offset
Register
PAE3
PAF3
PAE2
PAF2
PAE1
PAF1
PAE0
PAF0
6158 drw08
(1)
(1)
(1)
(1)