IDT72T54252L6-7BB IDT, Integrated Device Technology Inc, IDT72T54252L6-7BB Datasheet - Page 23

• Manufacturer Part Number: IDT72T54252L6-7BB
• Description: IC FIFO DDR/SDR QUAD/DUAL 324BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T54252L6-7BB

• Function: Asynchronous
• Memory Size: 20K (1K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T54252L6-7BB

SIGNAL DESCRIPTIONS
INPUTS:
DATA INPUT BUS (D[39:0])
in Dual mode. In Quad mode, D[9:0] are data inputs for FIFO0, D[19:10] are
for FIFO1, D[29:20] are for FIFO2, and D[39:30] are for FIFO3. In Dual mode,
D[19:0] are data inputs for FIFO0 and D[39:20] are for FIFO2 for the 20-bit wide
data bus. D[9:0] are data inputs for FIFO0 and D[29:20] are data inputs for
FIFO2 for the 10-bit wide data bus.
MASTER RESET (MRS)
A master reset is initiated whenever the MRS input is taken to a LOW state. This
operation sets the internal read and write pointers of all FIFOs to the first location
in memory. The programmable almost empty flag will go LOW and the almost
full flags will go HIGH.
selected. This mode utilizes the empty and full status flags from the EF/OR and
FF/IR dual-purpose pin. During master reset, all empty flags will be set to LOW
and all full flags will be set to HIGH.
Through mode is selected. This mode utilizes the input read and output ready
status flags from the EF/OR and FF/IR dual-purpose pin. During master reset,
all input ready flags will be set to LOW and all output ready flags will be set to
HIGH.
PFM, FSEL[1:0] and FWFT/SI need to be defined before the master reset cycle.
During a master reset the output registers are initialized to all zeros. If the output
enables are LOW during master reset, then the output bus will be LOW. If the
output enable(s) are HIGH during master reset, then the output bus will be in
high-impedance. RCS has no affect on the data outputs during master reset. If
the output width OW is configured to x10 in Dual mode, then the unused outputs
Q[19:10] and Q[39:30] will be in high-impedance. A master reset is required
after power up before a write operation to any FIFO can take place. Master reset
is an asynchronous signal and thus the read and write clocks can be free-
running or idle during master reset. See Figure 10, Master Reset Timing, for
the associated timing diagram.
PARTIAL RESET (PRS0/1/2/3)
pointers of each individual FIFO inside the device without changing the FIFO's
configuration. There are four dedicated partial reset signals (two in Dual mode)
that each correspond to an individual FIFO. There are no restrictions as to when
partial reset can be performed in either operating modes.
location in memory, PAE goes LOW and PAF goes HIGH. Whichever timing
mode was active at the time of Partial Reset will remain active after Partial Reset.
If IDT Standard Mode is active, then FF will go HIGH and EF will go LOW. If
the First Word Fall Through mode is active, then OR will go HIGH and IR will
go LOW.
unchanged. The output registers are initialized to all zeros. All other
configurations set up during master reset remain unchanged. PRS is an
asynchronous signal. See Figure 11, Partial Reset Timing, for the associated
timing diagram.
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
The data input busses are 10 bits wide in Quad mode and 20 or 10-bits wide
There is a single master reset available for all internal FIFOs in this device.
If FWFT/SI signal is LOW during master reset then IDT Standard mode is
If FWFT/SI signal is HIGH during master reset, then the First Word Fall
All device configuration pins such as MD, OW, IW, WDDR, RDDR, IOSEL,
A partial reset is a means by which the user can reset both the read and write
During partial reset, the internal read and write pointers are set to the first
Following Partial Reset, all values held in the offset registers remain
™
23
DDR/SDR FIFO
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
determines whether the device will operate in IDT Standard mode or First Word
Fall Through (FWFT) mode.
mode will be selected. This mode uses the Empty Flag (EF) to indicate whether
or not there are any words present in the FIFOs’ memory. It also uses the Full
Flag (FF) to indicate whether or not the FIFOs’ memory has any free space for
writing. In IDT Standard mode, every word read from the FIFOs, including the
first, must be requested using the Read Enable (REN), Read Chip Select (RCS)
and RCLK.
will be selected. This mode uses Output Ready (OR) to indicate whether or not
there is valid data in the output register. It also uses Input Ready (IR) to indicate
whether or not the FIFO's memory has any free space for writing. In other words,
they are the inverse of the empty and full flags. In the FWFT mode, the first word
written to an empty FIFO goes directly to data outputs after three RCLK rising
edges, provided that the first RCLK meets the t
a one RCLK cycle delay if t
enabled. Subsequent words must be accessed using the REN, RCS, and
RCLK.
of the reset recovery time (t
SI acts as a serial input for loading PAE and PAF offsets into the programmable
offset registers. The serial input is used in conjunction with SCLK, SWEN, SREN,
and SDO to access the offset registers. Serial programming using the FWFT/
SI pin functions the same way in both IDT Standard and FWFT modes.
WRITE CLOCK (WCLK0/1/2/3)
in this device depending on the mode selected, each corresponding to the
individual FIFOs in memory. A write can be initiated on the rising (or falling) edge
of the WCLK input. If the write double data rate (WDDR) mode pin is tied HIGH,
data will be written on both the rising and falling edge of WCLK0/1/2/3, provided
that WEN0/1/2/3 and WCS0/1/2/3 are enabled on the rising edge of WCLK 0/
1/2/3. If WDDR is tied LOW, data will be written only on the rising edge of WCLK0/
1/2/3 provided that WEN0/1/2/3 and WCS 0/1/2/3 are enabled. Each write
clock is completely independent from the others.
HIGH-to-LOW in DDR) transition of the write clock. It is permissible to stop the
write clocks, for asynchronous operations. Note that while the write clocks are
idle, the FF0/1/2/3 and PAF0/1/2/3 flags will not be updated unless the port is
operating in asynchronous timing mode (PFM=0). The write clocks can be
independent or coincident with one another. In Dual mode, the unused clocks
(WCLK1 and WCLK3) should be tied to GND.
WRITE ENABLE (WEN0/1/2/3)
device depending on the mode selected, one for each individual FIFO. When
the write enable input is LOW on the rising edge of WCLK in single data rate mode,
data is loaded on the rising edge of every WCLK cycle, provided the device
is not full and the write chip select (WCS) is enabled. The setup and hold times
are referenced with respect to the rising edge of WCLK only. When the write
enable input is LOW on the rising edge of WCLK in double data rate, data is
loaded into any of the FIFOs on the rising and falling edge of every WCLK cycle,
provided the device is not full and the write chip select (WCS) is enabled on the
This is a dual purpose pin. During master reset, the state of the FWFT/SI input
If FWFT/SI is LOW before the falling edge of master reset, then IDT Standard
If FWFT/SI is HIGH before the falling edge of master reset, then FWFT mode
The state of the FWFT/SI input must be kept at the present state for the minimum
There are a possible total of four write clocks (or two in Dual mode) available
Data setup and hold times must be met with respect to the LOW-to-HIGH (and
There are a total of four write enables (or two in Dual mode) available in this
SKEW
RSR
) after master reset. After this time, the FWFT/
is not met. REN and RCS do not need to be
COMMERCIAL AND INDUSTRIAL
SKEW
TEMPERATURE RANGES
parameter. There may be
FEBRUARY 11, 2009