IDT72T54252L6-7BB IDT, Integrated Device Technology Inc, IDT72T54252L6-7BB Datasheet - Page 20

• Manufacturer Part Number: IDT72T54252L6-7BB
• Description: IC FIFO DDR/SDR QUAD/DUAL 324BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T54252L6-7BB

• Function: Asynchronous
• Memory Size: 20K (1K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T54252L6-7BB

FIRST WORD FALL THROUGH MODE (FWFT)
outlined in Table 4, Status Flags for FWFT Mode. To write data into to the FIFO,
WEN, and WCS must be LOW. Data presented to the DATA IN lines will be
clocked into the FIFO on subsequent transitions of WCLK. After the first write is
performed, the Output Ready (OR) flag will go LOW. Subsequent writes will
continue to fill up the FIFO. PAE will go HIGH after n + 2 words have been loaded
into the FIFO, where n is the empty offset value. The default setting for these
values are listed in Table 4, Status Flags for FWFT Mode. This parameter is
also user programmable as described in the Serial Writing and Reading of Offset
Registers section.
cause the Programmable Almost-Full flag (PAF) to go LOW. Again, if no reads
are performed, the PAF will go LOW after (32,769-m) writes for the IDT72T54242,
(65,537-m) writes for the IDT72T54252, and (131,073-m) writes for the
IDT72T54262. In x20 dual mode, PAF will go LOW after (16,385-m) writes for
the IDT72T54242, (32,769-m) writes for the IDT72T54252, and (65,537-m)
writes for the IDT72T54262. The offset “m” is the full offset value. The default
setting for these values are listed in Table 4, Status Flags for FWFT Mode. This
parameter is also user programmable. See the section on serial writing and
reading of offset registers for details.
TABLE 3 — STATUS FLAGS FOR IDT STANDARD MODE
TABLE 4 — STATUS FLAGS FOR FWFT MODE
NOTE:
1. See Table 2 for values for n, m. Values n,m may be different for each FIFO.
NOTE:
1. See Table 2 for values for n, m. Values n,m may be different for each FIFO.
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
In this mode, the status flags OR, IR, PAE, and PAF operate in the manner
Continuing to write data into the FIFO without performing read operations will
Number of
Words in
FIFO
Number of
Words in
FIFO
IDT72T54242
Dual mode
IW/OW = x20
IDT72T54242
Dual mode
IW/OW = x20
16,384 - (m) to 16,383
16,385 - (m) to 16,384
1 to n+1
16,384
16,385
1 to n
0
0
IDT72T54242
Quad mode or Dual mode
IW/OW = x10
or
IDT72T54252
Dual mode IW/OW = x20
IDT72T54242
Quad mode or Dual mode
IW/OW = x10
or
IDT72T54252
Dual mode IW/OW = x20
32,768 - (m) to 32,767
32,769 - (m) to 32,768
1 to n+1
32,768
32,769
1 to n
0
0
™
IDT72T54252
Quad mode or Dual mode
IW/OW = x10
or
IDT72T54262
Dual mode IW/OW = x20
IDT72T54252
Quad mode or Dual mode
IW/OW = x10
or
IDT72T54262
Dual mode IW/OW = x20
20
DDR/SDR FIFO
65,536 - (m) to 65,535
65,537 - (m) to 65,536
operations. If no reads are performed after a reset, IR will go LOW after D writes
to the FIFO, where D = 32,769 writes for the IDT72T54242, 65,537 writes for
the IDT72T54252, and 131,073 writes for the IDT72T54262. In x20 dual mode,
FF will go LOW after 16,385 writes for the IDT72T54242, 32,769 writes for the
IDT72T54252, and 65,537 writes for the IDT72T54262.
read operations will cause PAF to go HIGH at the conditions described in Table
4, Status Flags for FWFT Mode. If further read operations occur without write
operations, PAE will go LOW when there are n words in the FIFO, where n is
the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO, the OR will
go HIGH inhibiting further read operations. REN is ignored when the FIFO is
empty, but RCS will continue to determine whether or not the output is in high-
impedance.
and the IR flag output is double register-buffered. Relevant timing diagrams for
FWFT mode can be found in Figure 19, 20, 21, 22 and 24.
When the FIFO is full, the Input Ready (IR) will go LOW, inhibiting further write
If the FIFO is full, the first read operation will cause IR to go HIGH. Subsequent
When configured in FWFT mode, the OR flag output is triple register-buffered
1 to n+1
65,536
65,537
1 to n
0
0
IDT72T54262
Quad mode or Dual mode
IW/OW = x10
IDT72T54262
Quad mode or Dual mode
IW/OW = x10
131,072 - (m) to 131,071
131,073 - (m) to 131,072
1 to n+1
131,072
131,073
1 to n
0
0
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009
FF PAF PAE EF
IR
H
H
H
L
L
L
L
H
PAF PAE OR
H
H
L
L
H
H
L
L
L
L
H
H
L
L
H
H
6158 drw09
L
H
H
H
H
L
L
L