IDT72T54252L6-7BB IDT, Integrated Device Technology Inc, IDT72T54252L6-7BB Datasheet - Page 21

• Manufacturer Part Number: IDT72T54252L6-7BB
• Description: IC FIFO DDR/SDR QUAD/DUAL 324BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T54252L6-7BB

• Function: Asynchronous
• Memory Size: 20K (1K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T54252L6-7BB

SELECTABLE MODES
mode. In the Quad mode there are four independent FIFOs available, with the
input and output bus widths set to 10 bits wide for each FIFO. A total of eight
independent clock inputs are available– four RCLKs and four WCLKs. Each
FIFO has independent read and write controls, output enable controls, as well
as individual status flags EF/OR, FF/IR, PAE, and PAF. Also available are echo
outputs ERCLK and EREN for each individual FIFO to aid high-speed operation
where synchronizing data is critical.
and output bus widths each selectable between x10 or x20. Bus-matching is
available in this mode, allowing for more flexibility. A total of four independent
clock inputs are available, two RCLKs and two WCLKs. Each FIFO has
independent read and write controls– output enable controls, as well as
individual status flags EF/OR, FF/IR, PAE, and PAF. Also available are echo
outputs ERCLK and EREN for each individual FIFO to aid high-speed operation
where synchronizing data is critical.
HSTL/LVTTL I/O
HSTL/eHSTL operation. If the IOSEL pin is HIGH during master reset, then all
applicable LVTTL or HSTL signals will be configured for HSTL/eHSTL
operating voltage levels. To select between HSTL or eHSTL V
driven to 1.5V or 1.8V respectively. Typically a logic HIGH in HSTL would be
V
HSTL signals will be configured for LVTTL operating voltage levels. In this
configuration V
NOTE:
1. In Dual mode, not all available signals will be used. Signals with a designation of 1 and 3 are not used.
TABLE 5 — I/O VOLTAGE LEVEL ASSOCIATIONS
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
REF
This device is capable of operating in two different modes: Quad mode or Dual
In the Dual mode there are two independent FIFOs available, with the input
The inputs and outputs of this device can be configured for either LVTTL or
If the IOSEL pin is LOW during master reset, then all applicable LVTTL or
D[39:0]
WCLK0/1/2/3
WEN0/1/2/3
WCS0/1/2/3
FF/IR0/1/2/3
PAF0/1/2/3
+ 0.2V and a logic LOW would be V
Write Port
REF
must be set to GND. Table 5 illustrates which pins are and
Q[39:0]
RCLK0/1/2/3
REN0/1/2/3
RCS0/1/2/3
EF/OR0/1/2/3
OE0/1/2/3
PAE0/1/2/3
ERCLK0/1/2/3
EREN0/1/2/3
Read Port
REF
– 0.2V.
LVTTL/HSTL/eHSTL SELECT
TCK
TRST
TMS
TDI
TDO
JTAG
REF
must be
™
21
DDR/SDR FIFO
are not associated with this feature. Note that all “Static Pins” must be tied to V
or GND. These pins are LVTTL only and are purely device configuration pins.
Note the IOSEL pin should be tied HIGH or LOW and cannot toggle before and
after master reset.
BUS MATCHING
capability such that the input and output busses can each be either 10 bits or
20 bits wide. The bus width of both the input and output port is determined during
master reset using the input (IW) and output (OW) widths setup pins. The selected
port width is applied to both FIFO ports, such that both FIFOs will be configured
for either x10 or x20 bus widths. When writing or reading data from a FIFO the
number of memory locations available to be read will depend on the bus width
selected and the density of the device.
of 32,768 x 10 for the IDT72T54242, 65,536 x 10 for the IDT72T54252, or
131,072 x 10 for the IDT72T54262. If the write/read ports are 20 bits wide, this
provides the user with a FIFO depth of 16,384 x 20 for the IDT72T54242,
32,768 x 20 for the IDT72T54252, or 65,536 x 20 for the IDT72T54262. The
FIFO depths will always have a fixed density of 327,680 bits for the IDT72T54242,
655,360 bits for the IDT72T54252 and 1,310,072 bits for the IDT72T54262
regardless of bus-width configuration on the write/read port. When the device
is operating in double data rate, the word is twice as large as in single data rate
since one word consists of both the rising and falling edge of clock. Therefore
in DDR, the FIFO depths will be half of what it is mentioned above. For instance,
if the write/read port is 10 bits wide, the depth of each FIFO is 16,384 x 10 for
the IDT72T54242, 32,768 x 10 for the IDT72T54252, or 65,536 x 10 for the
IDT72T54262. See Figure 5, Bus-Matching in Dual mode for more information.
FSEL[1:0]
PD
MRS
PRS0/1/2/3
FWFT/SI
Signal Pins
In the Dual mode operation, the write and read port have bus-matching
If the write/read ports are 10 bits wide, this provides the user with a FIFO depth
Serial Clock Port
SCLK
SREN
SWEN
FWFT/SI
SDO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
STATIC CMOS SIGNALS
IOSEL
IW
OW
MD
PFM
RDDR
WDDR
FEBRUARY 11, 2009
Static Pins
CC