IDT72T54252L6-7BB IDT, Integrated Device Technology Inc, IDT72T54252L6-7BB Datasheet - Page 3

• Manufacturer Part Number: IDT72T54252L6-7BB
• Description: IC FIFO DDR/SDR QUAD/DUAL 324BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T54252L6-7BB

• Function: Asynchronous
• Memory Size: 20K (1K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T54252L6-7BB

Features ......................................................................................................................................................................................................................... 1
Description ...................................................................................................................................................................................................................... 4
Pin Configuration ............................................................................................................................................................................................................. 6
Pin Descriptions ............................................................................................................................................................................................................... 7
Device Characteristics ................................................................................................................................................................................................... 11
DC Electrical Characteristics .......................................................................................................................................................................................... 12
AC Electrical Characteristics ........................................................................................................................................................................................... 14
AC Test Conditions ........................................................................................................................................................................................................ 15
Functional Description ................................................................................................................................................................................................... 17
Signal Descriptions ........................................................................................................................................................................................................ 23
JTAG Timing Specifications ............................................................................................................................................................................................ 29
Table 1 — Device Configuration .................................................................................................................................................................................... 17
Table 2 — Default Programmable Flag Offsets ................................................................................................................................................................ 17
Table 3 — Status Flags for IDT Standard mode ............................................................................................................................................................. 20
Table 4 — Status Flags for FWFT mode ........................................................................................................................................................................ 20
Table 5 — I/O Voltage Level Associations ....................................................................................................................................................................... 21
Table 6 — T
Figure 1. Quad/Dual Block Diagram ................................................................................................................................................................................ 5
Figure 2a. AC Test Load ................................................................................................................................................................................................ 15
Figure 2b. Lumped Capacitive Load, Typical Derating ................................................................................................................................................... 15
Figure 3. Programmable Flag Offset Programming Methods ........................................................................................................................................... 18
Figure 4. Offset Registers Serial Bit Sequence ................................................................................................................................................................ 19
Figure 5. Bus-Matching in Dual mode ............................................................................................................................................................................ 22
Figure 6. Echo Read Clock and Data Output Relationship .............................................................................................................................................. 27
Figure 7. Standard JTAG Timing ................................................................................................................................................................................... 28
Figure 8. JTAG Architecture ........................................................................................................................................................................................... 29
Figure 9. TAP Controller State Diagram ......................................................................................................................................................................... 30
Figure 10. Master Reset Timing ..................................................................................................................................................................................... 33
Figure 11. Partial Reset Timing ...................................................................................................................................................................................... 34
Figure 12. Write Cycle and Full Flag Timing (Quad mode, IDT Standard mode, SDR to SDR) ....................................................................................... 35
Figure 13. Write Cycle and Full Flag Timing (Quad mode, IDT Standard mode, DDR to DDR) ....................................................................................... 36
Figure 14. Write Cycle and Full Flag Timing (Dual mode, IDT Standard mode, DDR to SDR, x10 In to x20 Out) ............................................................ 37
Figure 15. Write Cycle and Full Flag (Dual mode, IDT Standard mode, SDR to DDR, x20 In to x10 Out) ....................................................................... 38
Figure 16. Write Cycle and Output Ready Timing (Quad mode, FWFT mode, SDR to SDR) .......................................................................................... 39
Figure 17. Write Cycle and Output Ready Timing (Quad mode, FWFT mode, DDR to DDR) .......................................................................................... 40
Figure 18. Read Cycle, Output Enable and Empty Flag Timing (Quad mode, IDT Standard mode, SDR to SDR) ........................................................... 41
Figure 19. Read Cycle, Output Enable and Empty Flag Timing (Quad mode, IDT Standard mode, DDR to DDR) .......................................................... 42
Figure 20. Read Cycle and Empty Flag Timing (Dual mode, IDT Standard mode, DDR to SDR, x20 In to x10 Out) ....................................................... 43
Figure 21. Read Cycle and Empty Flag Timing (Dual mode, IDT Standard mode, SDR to DDR, x10 In to x20 Out) ....................................................... 44
Figure 22. Read Timing and Output Ready Flag (Quad mode, FWFT mode, SDR to SDR) ........................................................................................... 45
Figure 23. Read Timing and Output Ready Timing (Quad mode, FWFT mode, DDR to DDR) ........................................................................................ 46
Figure 24. Read Cycle and Read Chip Select (Quad mode, IDT Standard mode, SDR to SDR) .................................................................................... 47
Figure 25. Read Cycle and Read Chip Select Timing (Quad mode, FWFT mode, SDR to SDR) .................................................................................... 48
Figure 26. Echo Read Clock and Read Enable Operation (Quad mode, IDT Standard mode, DDR to DDR) ................................................................. 49
Figure 27. Echo RCLK and Echo Read Enable Operation (Quad mode, FWFT mode, SDR to SDR) ............................................................................. 50
Figure 28. Echo Read Clock and Read Enable Operation (Quad mode, IDT Standard mode, SDR to SDR) .................................................................. 51
Figure 29. Loading of Programmable Flag Registers (IDT Standard and FWFT modes) ................................................................................................ 52
Figure 30. Reading of Programmable Flag Registers (IDT Standard and FWFT modes) ................................................................................................ 52
Figure 32. Synchronous Programmable Almost-Empty Flag Timing (Quad mode, IDT Standard and FWFT mode, SDR to SDR) ................................... 53
Figure 31. Synchronous Programmable Almost-Full Flag Timing (Quad mode, IDT Standard and FWFT mode, SDR to SDR) ....................................... 53
Figure 33. Asynchronous Programmable Almost-Full Flag Timing (Quad mode, IDT Standard and FWFT mode, SDR to SDR) ...................................... 54
Figure 34. Asynchronous Programmable Almost-Empty Flag Timing (Quad mode, IDT Standard and FWFT mode, SDR to SDR) .................................. 54
Figure 35. Power Down Operation ................................................................................................................................................................................ 55
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
SKEW
Measurement ................................................................................................................................................................................... 27
Table of Contents
List of Figures
List of Tables
™
3
DDR/SDR FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009