IDT72T54252L6-7BB IDT, Integrated Device Technology Inc, IDT72T54252L6-7BB Datasheet - Page 7

• Manufacturer Part Number: IDT72T54252L6-7BB
• Description: IC FIFO DDR/SDR QUAD/DUAL 324BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T54252L6-7BB

• Function: Asynchronous
• Memory Size: 20K (1K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T54252L6-7BB

PIN DESCRIPTIONS
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
D[39:0]
EF0/1/2/3,
OR0/1/2/3
ERCLK0/1/2/3 Echo Read Clock
EREN0/1/2/3
FF0/1/2/3,
IR0/1/2/3
FSEL
[1:0]
FWFT/SI
IOSEL
IW
MD
MRS
OE0/1/2/3
OW
PAE0/1/2/3
PAF0/1/2/3
Symbol
Output Enable
Data Input Bus
Empty Flag 0/1/2/3
or Output Ready
Flags 0/1/2/3
0/1/2/3
Echo Read Enable
0/1/2/3
Full Flags 0/1/2/3 or HSTL-LVTTL These are the Full Flags (IDT Standard mode) and Input Ready Flags (FWFT mode) corresponding
Input Ready Flags
0/1/2/3
Flag Select
First Word Fall
Through/ Serial
Input
I/O Select
Input Width
Mode
Master Reset
0/1/2/3
Output Width
Programmable
Almost-Empty
Flags 0/1/2/3
Programmable
Almost-Full Flags
0/1/2/3
Name
HSTL-LVTTL These are the data inputs for the device. Data is written into the part via these inputs using the respective
HSTL-LVTTL These are the Empty Flags (IDT Standard mode) or Output Ready Flag (FWFT mode) corresponding
HSTL-LVTTL These are the echo clock outputs corresponding to each of the four FIFOs on the read port. The
HSTL-LVTTL These are the echo read enable outputs corresponding to each of the four FIFOs on the read port.
HSTL-LVTTL Flag select default offset pins. During master reset, the FSEL pins are used to select one of four default
HSTL-LVTTL During Master Reset, FWFT=1 selects First Word Fall Through mode, FWFT=0 selects IDT Standard
HSTL-LVTTL This input provides a full device reset. All set-up pins are latched based on a master reset operation.
HSTL-LVTTL These are the output enables corresponding to each individual FIFO on the read port. All data outputs
HSTL-LVTTL These are the programmable almost empty flags that can be used as an early indicator for the empty
HSTL-LVTTL These are the programmable almost full flags that can be used as an early indicator for the full
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
I/O Type
CMOS
CMOS
CMOS
CMOS
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
(2)
(2)
(2)
(2)
(1)
(1)
(1)
(1)
(1)
(1)
state of FSEL0 and FSEL1 during master reset. The PAE offset value can also be written and read
write port clocks and enables. In Quad mode, these inputs provide four separate busses to the four
separate FIFOs. D[9:0] is FIFO[0], D[19:10] is FIFO[1], D[29:20] is FIFO[2], D[39:30] is FIFO[3].
In Dual mode, these inputs provide two separate busses to the two separate FIFOs. D[19:0] is FIFO[0],
D[39:20] is FIFO[2]. Any unused inputs should be tied to GND.
to each of the four FIFOs on the read port. If Dual mode is selected EF1/OR1 and EF3/OR3 are
not used and can be left floating.
echo read clock is guaranteed to transition after the slowest output data switching. If Dual mode is
selected ERCLK1 and ERCLK3 are not used and can be left floating
The echo read enable is synchronous to the RCLK input and is active when a read operation has
occurred and a new word has been placed onto the data output bus. If Dual mode is selected EREN1
and EREN3 are not used and can be left floating.
to each of the four FIFOs on the read port. If Dual mode is selected FF1/IR1 and FF3/IR3 are not
used and can be left floating.
PAE and PAF offsets. Both the PAE and the PAF offsets are programmed to the same value. Values
are: 00 = 7; 01 = 63; 10 = 127; 11 = 1023. The offset value selected is supplied to all internal FIFOs.
mode. After Master Reset this pin is used for the Serial Data input for the programming of the PAE and
PAF flag's offset registers.
This input determines whether the inputs will operate in LVTTL or HSTL/eHSTL mode. If IOSEL
pin is HIGH, then all inputs and outputs that are designated "LVTTL or HSTL" in this section will be
set to HSTL. If IOSEL is LOW then LVTTL is selected. This signal must be tied to either V
for proper operation.
If Dual mode is selected , this pin is used during master reset to select the input word width bus size
for the device. 0 = x10; 1 = x20. If Quad mode is selected the input word width will be x10 regardless
of IW. IW must be tied to V
This mode selection pin is used during master reset to select either Quad or Dual mode operation.
A HIGH on this pin selects Quad mode, a LOW selects Dual mode.
Read and write pointers will be reset to the first location memory. All flag offsets are cleared and
reset to default values determined by FSEL[1:0].
will be placed into High Impedance if this pin is High. These inputs are asynchronous. If Dual mode
is selected OE1 and OE3 are not used and should be tied to V
If Dual mode is selected, this pin is used during master reset to select the output word width bus size
for the device. 0 = x10; 1 = x20. If Quad mode is selected the output word width will be x10 regardless
of OW. OW must be tied to V
boundary of each FIFO. The PAE flags can be set to one of four default offsets determined by the
from serially by either the JTAG port or the serial programming pins (SCLK, SI, SDO, SWEN, SREN).
This flag can operate in synchronous or asynchronous mode depending on the sate of the PFM pin
during master reset. If Dual mode is selected PAE1 and PAE3 are not used and can be left floating.
boundary of each FIFO. The PAF flags can be set to one of four default offsets determined by the
state of FSEL0 and FSEL1 during master reset. The PAF offset value can also be written and read
from serially by either the JTAG port or the serial programming pins (SCLK, SI, SDO, SWEN, SREN).
™
7
DDR/SDR FIFO
CC
CC
or GND and cannot be left floating.
or GND and cannot be left floating.
Description
COMMERCIAL AND INDUSTRIAL
CC
.
TEMPERATURE RANGES
FEBRUARY 11, 2009
CC
or GND