IDT72T54252L6-7BB IDT, Integrated Device Technology Inc, IDT72T54252L6-7BB Datasheet - Page 8

• Manufacturer Part Number: IDT72T54252L6-7BB
• Description: IC FIFO DDR/SDR QUAD/DUAL 324BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T54252L6-7BB

• Function: Asynchronous
• Memory Size: 20K (1K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T54252L6-7BB

PIN DESCRIPTIONS (CONTINUED)
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
PAF0/1/2/3
(Continued)
PD
PFM
PRS0/1/2/3
Q[39:0]
RCLK0/1/2/3
RCS0/1/2/3
REN0/1/2/3
RDDR
SCLK
SDO
SREN
SWEN
Symbol
Programmable
Almost-Full Flags0-3 OUTPUT
Power Down
Programmable
Flag Mode
Partial Reset
Data Output Bus
Read Clock 0/1/2/3 HSTL-LVTTL These are the clock inputs corresponding to each of the four FIFOs on the read port. If Dual mode
Read Chip Select
Read Enable
Read Port DDR
Serial Clock
Serial Data
Serial Read Enable HSTL-LVTTL When SREN is brought LOW before the rising edge of SCLK, the contents of the PAE and PAF
Serial Write Enable
Name
HSTL-LVTTL This flag can operate in synchronous or asynchronous mode depending on the sate of the PFM pin
HSTL-LVTTL This input provides considerable power saving in HSTL/eHSTL mode. If this pin is low, the input
HSTL-LVTTL These are the partial reset inputs for each internal FIFO. The read, write, flag pointers, and output
HSTL-LVTTL These are the Data Outputs for the device. Data is read from the part via these outputs using the
HSTL-LVTTL These are the read chip select inputs corresponding to each of the four FIFOs on the read port. This
HSTL-LVTTL These are the read enable inputs corresponding to each of the four FIFOs on the read port. In SDR,
HSTL-LVTTL Serial clock for writing and reading the PAE and PAF offset registers. On the rising edge of each
HSTL-LVTTL On each rising edge of SCLK when SWEN is LOW, data from the FWFT/SI pin is serially loaded
OUTPUT
OUTPUT
I/O Type
CMOS
CMOS
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
LVTTL
INPUT
INPUT
INPUT
(2)
(2)
(1)
(1)
(1)
during master reset. If Dual mode is selected PAF1 and PAF3 are not used and can be left floating.
level translators for all the data input pins, clocks and non-essential control pins are turned off.
When PD is brought high, power-up sequence timing will have to be adhered to before the inputs
will be recognized. It is essential that the user respect these conditions when powering down the
part and powering up the part, so as to not produce runt pulses or glitches on the clocks if the clocks
are free running. PD does not provide any power consumption savings when the inputs are
configured for LVTTL.
During master reset, a HIGH on PFM selects synchronous PAE/PAF flag timing, a Low during
master reset selects asynchronous PAE/PAF flag timing. This pin controls all PAE/PAF flag outputs.
registers will all be set to zero when partial reset is activated. During partial reset, the existing mode
(IDT or FWFT), input/output bus width and rate mode, and the programmable flag settings are all
retained. If Dual mode is selected, PRS1 and PRS3 are not used and should be tied to V
respective read port clocks and enables. In Quad mode, these outputs provide four separate busses
from the four separate FIFO's. Q[9:0] is FIFO[0], Q[19:10] is FIFO[1], Q[29:20] is FIFO[2], Q[39:30]
is FIFO[3]. In Dual mode these outputs provide two separate busses from the two separate FIFO's.
Q[19:0] is FIFO[0] and Q[39:20] is FIFO[2].
is selected then RCLK1 and RCLK3 are not used and should be tied to GND. In SDR mode data
will be accessed on the rising edge of RCLK when REN and RCS are LOW at the rising edge of RCLK.
In DDR mode data will be accessed on both rising and falling edge of RCLK when REN is LOW.
pin provides synchronous control of the read port and high impedance control of the output data bus.
care, if OE is LOW the data inputs will be in Low-Impedance regardless of the state of RCS. If Dual
mode is selected then RCS1 and RCS3 are not used and should be tied to V
when this signal (and RCS) are LOW data will be sent from the FIFO memory to the output bus on
every rising edge of RCLK. In DDR mode, data will be accessed on both rising and falling edges
of RCLK. Note in DDR mode the REN and RCS are only sampled on the rising edge of RCLK. New
data will always begin from the rising edge not the falling edge of RCLK. If Dual mode is selected
then REN1 and REN3 are not used and should be tied to V
During master reset, this pin selects the output port to operate in DDR or SDR format. If RDDR is HIGH,
then a word is read on the rising and falling edge of the appropriate RCLK0, 1, 2 and 3 input. If RDDR
is LOW, then a word is read only on the rising edge of the appropriate RCLK0, 1, 2 and 3 inputs.
SCLK, when SWEN is low, one bit of data is shifted into the PAE and PAF registers. On the rising edge
of each SCLK, when SREN is low, one bit of data is shifted out of the PAE and PAF offset registers.
The reading of the PAE and PAF registers is non-destructive. If programming of the PAE/PAF offset
registers are done via the JTAG port, this input must be tied to V
This output is used to read data from the programmable flag offset registers. It is used in conjunction
with the SREN and SCLK signals.
offset registers are copied to a serial shift register. While SREN is maintained LOW, on each rising
edge of SCLK, one bit of data is shifted out of this serial shift register through the SDO output pin.
If programming of the PAE/PAF offset registers is done via the JTAG port, this input must be tied HIGH.
into the PAE and PAF registers. If programming of the PAE/PAF offset registers is done via the
JTAG port, this input must be tied HIGH.
RCS is only sampled on the rising edge of RCLK. During master or partial reset this input is a don’t
™
8
DDR/SDR FIFO
Description
COMMERCIAL AND INDUSTRIAL
CC
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CC
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TEMPERATURE RANGES
FEBRUARY 11, 2009
CC
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CC
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