AD9251BCPZRL7 Analog Devices, Inc., AD9251BCPZRL7 Datasheet
AD9251BCPZRL7
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AD9251BCPZRL7 Summary of contents
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... Fax: 781.461.3113 AD9251 GND SDIO SCLK CS SPI ORA PROGRAMMING DATA D13A ADC D0A DCOA DRVDD AD9251 ORB D13B ADC D0B DCOB DIVIDE DUTY CYCLE MODE STABILIZER CONTROLS SYNC DCS PDWN DFS OE Figure 1. www.analog.com ©2009 Analog Devices, Inc. All rights reserved ...
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AD9251 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 DC Specifications ......................................................................... 4 AC Specifications .......................................................................... 5 Digital Specifications ...
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Preliminary Technical Data GENERAL DESCRIPTION The AD9251 is a monolithic, dual channel 1.8 V supply, 14-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC), featuring a high performance sample-and- hold circuit and on-chip voltage reference. The product uses a multistage ...
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AD9251 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing ...
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Preliminary Technical Data AC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 2. 1 Parameter SIGNAL-TO-NOISE-RATIO (SNR) ...
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... MHz IN TWO-TONE SFDR MHz (−7 dBFS), 32 MHz (−7 dBFS) IN CROSSTALK ANALOG INPUT BANDWIDTH 1 A complete set of definitions on how these tests were completed can be found in the AN-835 application note from Analog Devices, Inc. AD9251-20/AD9251-40 Temp Min Typ Max Min 25°C 95 ...
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Preliminary Technical Data DIGITAL SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS ...
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AD9251 SWITCHING SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 4. Parameter CLOCK INPUT PARAMETERS Input Clock ...
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Preliminary Technical Data VIN CLK+ CLK– DCOA/DCOB CH A/CH B DATA TIMING SPECIFICATIONS Table 5. Parameter Conditions SYNC TIMING REQUIREMENTS t SYNC to rising edge of CLK setup time SSYNC t SYNC to rising edge of CLK hold time HSYNC ...
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AD9251 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter ELECTRICAL AVDD to AGND DRVDD to AGND VIN+A/VIN+B, VIN−A/VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VREF to AGND SENSE to AGND VCM to AGND RBIAS to AGND CS to AGND ...
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Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS (LSB) D0B DRVDD NOTES CONNECT 2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. Table 8. ...
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AD9251 Pin No. Mnemonic Description 61, 62 VIN±B Channel B Analog Inputs. Preliminary Technical Data Rev Page ...
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Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0dBFS, DCS disabled, unless otherwise noted. Figure 6. AD9251-20 Single-Tone FFT with ...
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AD9251 Figure 12. AD9251-80 Single-Tone FFT with f Figure 13. AD9251-80 Single-Tone FFT with f Figure 14. AD9251-80 Single-Tone SNR/SFDR vs. Input Amplitude (A with f = 9.7 MHz IN = 100 MHz Figure 15. AD9251-80 Single-Tone SNR/SFDR vs. Input ...
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Preliminary Technical Data Figure 18. AD9251-80 Two-Tone SFDR/IMD3 vs. Input Amplitude (A with f = 29.1 MHz 32.1 MHz, f IN1 IN2 Figure 19. AD9251-80 Two-Tone FFT with f = 29.1 MHz and f IN1 ) Figure 20. ...
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AD9251 EQUIVALENT CIRCUITS AVDD VIN ± x Figure 21. Equivalent Analog Input Circuit 5Ω CLK+ 15kΩ 15kΩ 5Ω CLK– Figure 22. Equivalent Clock Input Circuit AVDD DRVDD 30kΩ 380kΩ SDIO/DCS 30kΩ Figure 23. Equivalent SDIO/ODM Input Circuit 0.9V Rev. Pr ...
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Preliminary Technical Data DRVDD AVDD 30kΩ 350Ω CSB Figure 27. Equivalent CS Input Circuit AVDD 375Ω SENSE Figure 28. Equivalent SENSE Circuit VREF Figure 29. Equivalent VREF Circuit Rev. PrH | Page AD9251 AVDD 375Ω 7.5kΩ ...
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AD9251 THEORY OF OPERATION The AD9251 dual ADC design can be used for diversity reception of signals, where the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent ...
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Preliminary Technical Data Figure 31. SNR/SFDR vs. Common-Mode Voltage 30.5 MHz MSPS IN S Figure 32. SNR/SFDR vs. Common-Mode Voltage 9.7 MHz MSPS IN S Differential Input Configurations Optimum performance ...
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AD9251 0.1µF 2V p-p P 0.1µF ANALOG INPUT C D ANALOG INPUT 0.1µF 0.1µF 25Ω 0.1µF 25Ω 0.1µF Figure 36. Differential Double Balun Input Configuration V CC 0Ω 0.1µ 0.1µ ...
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Preliminary Technical Data VOLTAGE REFERENCE A stable and accurate voltage reference is built into the AD9251. The input range can be adjusted by varying the reference voltage applied to the AD9251, using either the internal reference or an externally applied ...
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AD9251 External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift charac- teristics. Figure 41 shows the typical drift characteristics of the internal reference in 1.0 ...
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Preliminary Technical Data If a low jitter clock source is not available, another option couple a differential PECL signal to the sample clock input pins, as shown in Figure 45. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516/AD9517 excellent jitter performance. 0.1µF ...
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AD9251 The clock input should be treated as an analog signal in cases in which aperture jitter may affect the dynamic range of the AD9251. Separate power supplies for clock drivers from the ADC output driver supplies to avoid modulating ...
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Preliminary Technical Data When using the SPI interface, the data outputs and DCO of each channel can be independently three-stated by using the output enable bar bit in Register 0x14. {Is this Bit 5 in Register 0x14?} TIMING The AD9251 ...
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AD9251 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9251 includes built-in test features designed to enable verification of the integrity of each channel as well as facilitate board level debugging. A built-in self-test (BIST) feature that verifies the integrity of ...
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Preliminary Technical Data CHANNEL/CHIP SYNCHRONIZATION The AD9251 has a SYNC input that offers the user flexible synchronization options for synchronizing the internal blocks. The clock divider sync feature is useful for guaranteeing synchro- nized sample clocks across multiple ADCs. The ...
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AD9251 SERIAL PORT INTERFACE (SPI) The AD9251 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and ...
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Preliminary Technical Data CONFIGURATION WITHOUT THE SPI In applications that do not interface to the SPI control registers, the SDIO/DCS pin, the SCLK/DFS pin, the OE pin, and the PDWN pin serve as standalone CMOS-compatible control pins. When the device ...
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AD9251 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table (see Table 16) has eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to ...
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Preliminary Technical Data MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 16 are not currently supported for this device. Table 16. Addr Register Bit 7 (Hex) Name (MSB) Bit 6 Chip Configuration Registers ...
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AD9251 Addr Register Bit 7 (Hex) Name (MSB) Bit 6 0x0E BIST enable Open 0x10 Offset adjust 8-bit device offset adjustment 7:0 (local) (local) Offset adjust in LSBs from +127 to −128 (twos complement format) 0x14 Output mode 00 = ...
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Preliminary Technical Data Addr Register Bit 7 (Hex) Name (MSB) Bit 6 (global) Reserved [6: 0x101 usr2 Enable OE Pin 31 (local) MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions controlled in Register 0x00 to Register 0xFF, ...
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AD9251 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9251 as a system recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. ...
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... AD9251BCPZRL7–65 –40°C to +85° AD9251BCPZ-40 –40°C to +85° AD9251BCPZRL7–40 –40°C to +85°C AD9251BCPZ- –40°C to +85° AD9251BCPZRL7–20 –40°C to +85°C 1, AD9251-80EBZ 1, AD9251-65EBZ 1, AD9251-40EBZ 1, AD9251-20EBZ RoHS Compliant Part. 2 The exposed paddle (Pin 0) is the only GND connection on the chip and must be connected to the PCB AGND ...
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... AD9251 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07938-0-4/09(PrH) Preliminary Technical Data Rev. PrH | Page ...