AD9251BCPZRL7 Analog Devices, Inc., AD9251BCPZRL7 Datasheet - Page 27
AD9251BCPZRL7
Manufacturer Part Number
AD9251BCPZRL7
Description
14-bit, 20 Msps/40 Msps/65 Msps/80 Msps, 1.8 V Dual Analog-to-digital Converter
Manufacturer
Analog Devices, Inc.
Datasheet
1.AD9251BCPZRL7.pdf
(36 pages)
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Preliminary Technical Data
CHANNEL/CHIP SYNCHRONIZATION
The AD9251 has a SYNC input that offers the user flexible
synchronization options for synchronizing the internal blocks.
The clock divider sync feature is useful for guaranteeing synchro-
nized sample clocks across multiple ADCs. The signal monitor
block can also be synchronized using the SYNC input, allowing
properties of the input signal to be measured during a specific
time period. The input clock divider can be enabled to synchronize
on a single occurrence of the SYNC signal or on every occurrence.
Rev. PrH | Page 27 of 36
The signal monitor block is synchronized on every SYNC
input signal.
The SYNC input is internally synchronized to the sample clock;
however, to ensure there is no timing uncertainty between multiple
parts, the SYNC input signal should be externally synchronized to
the input clock signal, meeting the setup and hold times shown
in Table 5. Drive the SYNC input using a single-ended CMOS-
type signal.
AD9251
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