AD9251BCPZRL7 Analog Devices, Inc., AD9251BCPZRL7 Datasheet - Page 23

• Manufacturer Part Number: AD9251BCPZRL7
• Description: 14-bit, 20 Msps/40 Msps/65 Msps/80 Msps, 1.8 V Dual Analog-to-digital Converter
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 45. The
AD9513/AD9514/AD9515/AD9516/AD9517
excellent jitter performance.
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 46. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517
clock drivers offer excellent jitter performance.
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, the CLK+ pin should be driven directly from a
CMOS gate, and the CLK− pin should be bypassed to ground
with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see
Figure 47).
Input Clock Divider
The AD9251 contains an input clock divider with the ability to
divide the input clock by integer values between 1 and 8. If a
divide ratio other than 1 is selected, the duty cycle stabilizer is
automatically enabled.
The AD9251 clock divider can be synchronized using the
external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the
clock divider to be resynchronized on every SYNC signal or
only on the first SYNC signal after the register is written. A
valid SYNC causes the clock divider to reset to its initial state.
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
INPUT
INPUT
INPUT
INPUT
INPUT
Figure 47. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
50kΩ
50kΩ
Figure 45. Differential PECL Sample Clock (Up to 625 MHz)
Figure 46. Differential LVDS Sample Clock (Up to 625 MHz)
50Ω
1
50Ω RESISTOR IS OPTIONAL.
0.1µF
1
0.1µF
0.1µF
50kΩ
0.1µF
0.1µF
50kΩ
V
CC
1kΩ
1kΩ
LVDS DRIVER
PECL DRIVER
CMOS DRIVER
AD951x
AD951x
AD951x
240Ω
AD9510/AD9511/AD9512/
0.1µF
OPTIONAL
240Ω
100Ω
100Ω
100Ω
39kΩ
0.1µF
0.1µF
0.1µF
0.1µF
clock drivers offer
0.1µF
CLK+
CLK–
CLK+
CLK–
CLK+
CLK–
ADC
ADC
ADC
Rev. PrH | Page 23 of 36
This synchronization feature allows multiple parts to have their
clock dividers aligned to guarantee simultaneous input
sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9251 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD9251. Noise and distortion perform-
ance are nearly flat for a wide range of duty cycles with the DCS
on, as shown in Figure X.
Jitter in the rising edge of the input is still of paramount concern
and is not easily reduced by the internal stabilization circuit.
The duty cycle control loop does not function for clock rates
less than 20 MHz nominally. The loop has a time constant
associated with it that must be considered in applications in
which the clock rate can change dynamically. A wait time of
1.5 μs to 5 μs is required after a dynamic clock frequency increase
or decrease before the DCS loop is relocked to the input signal.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR from the low
frequency SNR (SNR
to jitter (t
In the previous equation, the rms aperture jitter represents the
clock input jitter specification. IF undersampling applications
are particularly sensitive to jitter, as illustrated in Figure 48.
SNR
80
75
70
65
60
55
50
45
HF
1
JRMS
= −10 log[(2π × f
) can be calculated by
Figure 48. SNR vs. Input Frequency and Jitter
LF
) at a given input frequency (f
10
FREQUENCY (MHz)
INPUT
× t
JRMS
)
100
2
+ 10
3.0ps
(
−
SNR
0.05ps
0.2ps
0.5ps
1.0ps
1.5ps
2.0ps
2.5ps
LF
AD9251
INPUT
/
10
)
]
1k
) due